From: "Ghannam, Yazen" <Yazen.Ghannam@amd.com>
To: "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>
Cc: "Ghannam, Yazen" <Yazen.Ghannam@amd.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"bp@alien8.de" <bp@alien8.de>
Subject: [PATCH v3 7/8] EDAC/amd64: Support Asymmetric Dual-Rank DIMMs
Date: Thu, 22 Aug 2019 00:00:02 +0000 [thread overview]
Message-ID: <20190821235938.118710-8-Yazen.Ghannam@amd.com> (raw)
In-Reply-To: <20190821235938.118710-1-Yazen.Ghannam@amd.com>
From: Yazen Ghannam <yazen.ghannam@amd.com>
Future AMD systems will support "Asymmetric" Dual-Rank DIMMs. These are
DIMMs where the ranks are of different sizes.
The even rank will use the Primary Even Chip Select registers and the
odd rank will use the Secondary Odd Chip Select registers.
Recognize if a Secondary Odd Chip Select is being used. Use the
Secondary Odd Address Mask when calculating the chip select size.
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
Link:
https://lkml.kernel.org/r/20190709215643.171078-8-Yazen.Ghannam@amd.com
v2->v3:
* Add check of csrow_nr before using secondary mask.
v1->v2:
* No change.
drivers/edac/amd64_edac.c | 18 +++++++++++++++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 26ce48fcaf00..4d1e6daa7ec4 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -790,9 +790,13 @@ static void debug_dump_dramcfg_low(struct amd64_pvt *pvt, u32 dclr, int chan)
#define CS_EVEN_PRIMARY BIT(0)
#define CS_ODD_PRIMARY BIT(1)
+#define CS_EVEN_SECONDARY BIT(2)
+#define CS_ODD_SECONDARY BIT(3)
-#define CS_EVEN CS_EVEN_PRIMARY
-#define CS_ODD CS_ODD_PRIMARY
+#define CS_EVEN (CS_EVEN_PRIMARY | CS_EVEN_SECONDARY)
+#define CS_ODD (CS_ODD_PRIMARY | CS_EVEN_SECONDARY)
+
+#define csrow_sec_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE)
static int f17_get_cs_mode(int dimm, u8 ctrl, struct amd64_pvt *pvt)
{
@@ -804,6 +808,10 @@ static int f17_get_cs_mode(int dimm, u8 ctrl, struct amd64_pvt *pvt)
if (csrow_enabled(2 * dimm + 1, ctrl, pvt))
cs_mode |= CS_ODD_PRIMARY;
+ /* Asymmetric Dual-Rank DIMM support. */
+ if (csrow_sec_enabled(2 * dimm + 1, ctrl, pvt))
+ cs_mode |= CS_ODD_SECONDARY;
+
return cs_mode;
}
@@ -1600,7 +1608,11 @@ static int f17_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc,
*/
dimm = csrow_nr >> 1;
- addr_mask_orig = pvt->csels[umc].csmasks[dimm];
+ /* Asymmetric Dual-Rank DIMM support. */
+ if ((csrow_nr & 1) && (cs_mode & CS_ODD_SECONDARY))
+ addr_mask_orig = pvt->csels[umc].csmasks_sec[dimm];
+ else
+ addr_mask_orig = pvt->csels[umc].csmasks[dimm];
/*
* The number of zero bits in the mask is equal to the number of bits
--
2.17.1
next prev parent reply other threads:[~2019-08-22 0:00 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-21 23:59 [PATCH v3 0/8] AMD64 EDAC fixes Ghannam, Yazen
2019-08-21 23:59 ` [PATCH v3 1/8] EDAC/amd64: Support more than two controllers for chip selects handling Ghannam, Yazen
2019-08-21 23:59 ` [PATCH v3 2/8] EDAC/amd64: Recognize DRAM device type with EDAC_CTL_CAP Ghannam, Yazen
2019-08-21 23:59 ` [PATCH v3 3/8] EDAC/amd64: Initialize DIMM info for systems with more than two channels Ghannam, Yazen
2019-08-21 23:59 ` [PATCH v3 4/8] EDAC/amd64: Find Chip Select memory size using Address Mask Ghannam, Yazen
2019-08-22 0:00 ` [PATCH v3 5/8] EDAC/amd64: Decode syndrome before translating address Ghannam, Yazen
2019-08-22 0:00 ` [PATCH v3 6/8] EDAC/amd64: Cache secondary Chip Select registers Ghannam, Yazen
2019-08-22 0:00 ` [RFC PATCH v3 08/10] EDAC/amd64: Gather hardware information early Ghannam, Yazen
2019-08-29 9:22 ` Borislav Petkov
2019-09-06 19:14 ` Ghannam, Yazen
2019-09-06 20:35 ` Borislav Petkov
2019-09-06 20:49 ` Ghannam, Yazen
2019-09-09 15:31 ` Borislav Petkov
2019-08-22 0:00 ` Ghannam, Yazen [this message]
2019-08-23 11:26 ` [PATCH v3 7/8] EDAC/amd64: Support Asymmetric Dual-Rank DIMMs Borislav Petkov
2019-08-23 13:27 ` Ghannam, Yazen
2019-08-23 15:11 ` Borislav Petkov
2019-08-22 0:00 ` [RFC PATCH v3 10/10] EDAC/amd64: Check for memory before fully initializing an instance Ghannam, Yazen
2019-08-22 18:51 ` [RFC PATCH v2] " Ghannam, Yazen
2019-08-22 0:00 ` [RFC PATCH v3 09/10] EDAC/amd64: Use cached data when checking for ECC Ghannam, Yazen
2019-08-22 0:50 ` [PATCH v3 0/8] AMD64 EDAC fixes Adam Borowski
2019-08-22 8:35 ` Borislav Petkov
2019-08-22 9:46 ` Adam Borowski
2019-08-22 9:55 ` Borislav Petkov
2019-08-22 18:54 ` Ghannam, Yazen
2019-08-23 15:28 ` Ghannam, Yazen
2019-08-23 15:37 ` Borislav Petkov
2019-08-26 14:19 ` Ghannam, Yazen
2019-08-26 14:59 ` Borislav Petkov
2019-08-26 15:05 ` Ghannam, Yazen
2019-08-22 18:48 ` [RFC PATCH v2] EDAC/amd64: Check for memory before fully initializing an instance Ghannam, Yazen
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