From: Jiaxun Yang <jiaxun.yang@flygoat.com>
To: linux-mips@vger.kernel.org
Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de,
jason@lakedaemon.net, maz@kernel.org,
linux-kernel@vger.kernel.org, robh+dt@kernel.org,
mark.rutland@arm.co, devicetree@vger.kernel.org,
Jiaxun Yang <jiaxun.yang@flygoat.com>
Subject: [PATCH 12/13] MIPS: Loongson64: Add generic dts
Date: Tue, 27 Aug 2019 16:53:01 +0800 [thread overview]
Message-ID: <20190827085302.5197-13-jiaxun.yang@flygoat.com> (raw)
In-Reply-To: <20190827085302.5197-1-jiaxun.yang@flygoat.com>
Add generic device dts for Loongson-3 devices.
They seems identical but will be different later.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/Kconfig | 4 +-
arch/mips/boot/dts/Makefile | 1 +
arch/mips/boot/dts/loongson/Makefile | 8 +
arch/mips/boot/dts/loongson/ls3-2nodes.dtsi | 8 +
arch/mips/boot/dts/loongson/ls3-4nodes.dtsi | 15 ++
arch/mips/boot/dts/loongson/ls3-cpus.dtsi | 150 ++++++++++++++++++
arch/mips/boot/dts/loongson/ls3-gs464.dtsi | 18 +++
arch/mips/boot/dts/loongson/ls3-gs464e.dtsi | 18 +++
.../boot/dts/loongson/ls3-rs780e-pch.dtsi | 35 ++++
arch/mips/boot/dts/loongson/ls3a-package.dtsi | 59 +++++++
.../boot/dts/loongson/ls3a1000_780e_1way.dts | 12 ++
.../boot/dts/loongson/ls3a1000_780e_2way.dts | 13 ++
.../boot/dts/loongson/ls3a1000_780e_4way.dts | 13 ++
.../boot/dts/loongson/ls3a2000_780e_1way.dts | 12 ++
.../boot/dts/loongson/ls3a2000_780e_2way.dts | 13 ++
.../boot/dts/loongson/ls3a2000_780e_4way.dts | 13 ++
.../boot/dts/loongson/ls3a3000_780e_1way.dts | 12 ++
.../boot/dts/loongson/ls3a3000_780e_2way.dts | 13 ++
.../boot/dts/loongson/ls3a3000_780e_4way.dts | 13 ++
arch/mips/boot/dts/loongson/ls3b-package.dtsi | 59 +++++++
.../mips/boot/dts/loongson/ls3b_780e_1way.dts | 13 ++
.../mips/boot/dts/loongson/ls3b_780e_2way.dts | 13 ++
22 files changed, 514 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/boot/dts/loongson/Makefile
create mode 100644 arch/mips/boot/dts/loongson/ls3-2nodes.dtsi
create mode 100644 arch/mips/boot/dts/loongson/ls3-4nodes.dtsi
create mode 100644 arch/mips/boot/dts/loongson/ls3-cpus.dtsi
create mode 100644 arch/mips/boot/dts/loongson/ls3-gs464.dtsi
create mode 100644 arch/mips/boot/dts/loongson/ls3-gs464e.dtsi
create mode 100644 arch/mips/boot/dts/loongson/ls3-rs780e-pch.dtsi
create mode 100644 arch/mips/boot/dts/loongson/ls3a-package.dtsi
create mode 100644 arch/mips/boot/dts/loongson/ls3a1000_780e_1way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3a1000_780e_2way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3a1000_780e_4way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3a2000_780e_1way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3a2000_780e_2way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3a2000_780e_4way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3a3000_780e_1way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3a3000_780e_2way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3a3000_780e_4way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3b-package.dtsi
create mode 100644 arch/mips/boot/dts/loongson/ls3b_780e_1way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3b_780e_2way.dts
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 92a2ee773a40..1c27c3a4e036 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -485,6 +485,8 @@ config MACH_LOONGSON64
select SYS_SUPPORTS_LITTLE_ENDIAN
select ZONE_DMA32
select SYS_SUPPORTS_ZBOOT
+ select USE_OF
+ select BUILTIN_DTB
help
This enables the support of Loongson-3A/3B/2-series-soc processors
@@ -3074,7 +3076,7 @@ endchoice
choice
prompt "Kernel command line type" if !CMDLINE_OVERRIDE
default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
- !MIPS_MALTA && \
+ !MACH_LOONGSON64 && !MIPS_MALTA && \
!CAVIUM_OCTEON_SOC
default MIPS_CMDLINE_FROM_BOOTLOADER
diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
index 1e79cab8e269..d429a69bfe30 100644
--- a/arch/mips/boot/dts/Makefile
+++ b/arch/mips/boot/dts/Makefile
@@ -4,6 +4,7 @@ subdir-y += cavium-octeon
subdir-y += img
subdir-y += ingenic
subdir-y += lantiq
+subdir-y += loongson
subdir-y += mscc
subdir-y += mti
subdir-y += netlogic
diff --git a/arch/mips/boot/dts/loongson/Makefile b/arch/mips/boot/dts/loongson/Makefile
new file mode 100644
index 000000000000..25dca8a89d5d
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/Makefile
@@ -0,0 +1,8 @@
+# SPDX_License_Identifier: GPL_2.0
+dtb-$(CONFIG_MACH_LOONGSON64) += ls3a1000_780e_1way.dtb ls3a1000_780e_2way.dtb ls3a1000_780e_4way.dtb \
+ ls3b_780e_1way.dtb ls3b_780e_2way.dtb \
+ ls3a2000_780e_1way.dtb ls3a2000_780e_2way.dtb ls3a2000_780e_4way.dtb \
+ ls3a3000_780e_1way.dtb ls3a3000_780e_2way.dtb ls3a3000_780e_4way.dtb
+
+
+obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/mips/boot/dts/loongson/ls3-2nodes.dtsi b/arch/mips/boot/dts/loongson/ls3-2nodes.dtsi
new file mode 100644
index 000000000000..3103a4f96f68
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/ls3-2nodes.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
+
+&cpu4 { status = "okay"; };
+&cpu5 { status = "okay"; };
+&cpu6 { status = "okay"; };
+&cpu7 { status = "okay"; };
+
+&scache1 { status = "okay"; };
diff --git a/arch/mips/boot/dts/loongson/ls3-4nodes.dtsi b/arch/mips/boot/dts/loongson/ls3-4nodes.dtsi
new file mode 100644
index 000000000000..be8cca52c072
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/ls3-4nodes.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/include/ "ls3-2nodes.dtsi"
+
+&cpu8 { status = "okay"; };
+&cpu9 { status = "okay"; };
+&cpu10 { status = "okay"; };
+&cpu11 { status = "okay"; };
+&cpu12 { status = "okay"; };
+&cpu13 { status = "okay"; };
+&cpu14 { status = "okay"; };
+&cpu15 { status = "okay"; };
+
+&scache2 { status = "okay"; };
+&scache3 { status = "okay"; };
diff --git a/arch/mips/boot/dts/loongson/ls3-cpus.dtsi b/arch/mips/boot/dts/loongson/ls3-cpus.dtsi
new file mode 100644
index 000000000000..7e4705cd8a7c
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/ls3-cpus.dtsi
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ /*
+ * Loongson-3 may have as many as 4 nodes, each node has 4 cores.
+ * Each core has its own pcache and cores in the same node share scache.
+ * CPU 0-3 should always exist in all the systems.
+ */
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ reg = <0x0>;
+ next-level-cache = <&scache0>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ reg = <0x1>;
+ next-level-cache = <&scache0>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ reg = <0x2>;
+ next-level-cache = <&scache0>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ reg = <0x3>;
+ next-level-cache = <&scache0>;
+ };
+
+ cpu4: cpu@4 {
+ status = "disabled";
+ device_type = "cpu";
+ reg = <0x4>;
+ next-level-cache = <&scache1>;
+ };
+
+ cpu5: cpu@5 {
+ status = "disabled";
+ device_type = "cpu";
+ reg = <0x5>;
+ next-level-cache = <&scache1>;
+ };
+
+ cpu6: cpu@6 {
+ status = "disabled";
+ device_type = "cpu";
+ reg = <0x6>;
+ next-level-cache = <&scache1>;
+ };
+
+ cpu7: cpu@7 {
+ status = "disabled";
+ device_type = "cpu";
+ reg = <0x7>;
+ next-level-cache = <&scache1>;
+ };
+
+ cpu8: cpu@8 {
+ status = "disabled";
+ device_type = "cpu";
+ reg = <0x8>;
+ next-level-cache = <&scache2>;
+ };
+
+ cpu9: cpu@9 {
+ status = "disabled";
+ device_type = "cpu";
+ reg = <0x9>;
+ next-level-cache = <&scache2>;
+ };
+
+ cpu10: cpu@a {
+ status = "disabled";
+ device_type = "cpu";
+ reg = <0xa>;
+ next-level-cache = <&scache2>;
+ };
+
+ cpu11: cpu@b {
+ status = "disabled";
+ device_type = "cpu";
+ reg = <0xb>;
+ next-level-cache = <&scache2>;
+ };
+
+ cpu12: cpu@c {
+ status = "disabled";
+ device_type = "cpu";
+ reg = <0xc>;
+ next-level-cache = <&scache3>;
+ };
+
+ cpu13: cpu@d {
+ status = "disabled";
+ device_type = "cpu";
+ reg = <0xd>;
+ next-level-cache = <&scache3>;
+ };
+
+ cpu14: cpu@e {
+ status = "disabled";
+ device_type = "cpu";
+ reg = <0xe>;
+ next-level-cache = <&scache3>;
+ };
+
+ cpu15: cpu@f {
+ status = "disabled";
+ device_type = "cpu";
+ reg = <0xf>;
+ next-level-cache = <&scache3>;
+ };
+
+ scache0: l2-cache0 {
+ compatible = "cache";
+ };
+
+ scache1: l2-cache1 {
+ status = "disabled";
+ compatible = "cache";
+ };
+
+ scache2: l2-cache2 {
+ status = "disabled";
+ compatible = "cache";
+ };
+
+ scache3: l2-cache3 {
+ status = "disabled";
+ compatible = "cache";
+ };
+ };
+
+ cpuintc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+};
diff --git a/arch/mips/boot/dts/loongson/ls3-gs464.dtsi b/arch/mips/boot/dts/loongson/ls3-gs464.dtsi
new file mode 100644
index 000000000000..54d7be042150
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/ls3-gs464.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+
+&cpu0 { compatible = "loongson,gs464"; };
+&cpu1 { compatible = "loongson,gs464"; };
+&cpu2 { compatible = "loongson,gs464"; };
+&cpu3 { compatible = "loongson,gs464"; };
+&cpu4 { compatible = "loongson,gs464"; };
+&cpu5 { compatible = "loongson,gs464"; };
+&cpu6 { compatible = "loongson,gs464"; };
+&cpu7 { compatible = "loongson,gs464"; };
+&cpu8 { compatible = "loongson,gs464"; };
+&cpu9 { compatible = "loongson,gs464"; };
+&cpu10 { compatible = "loongson,gs464"; };
+&cpu11 { compatible = "loongson,gs464"; };
+&cpu12 { compatible = "loongson,gs464"; };
+&cpu13 { compatible = "loongson,gs464"; };
+&cpu14 { compatible = "loongson,gs464"; };
+&cpu15 { compatible = "loongson,gs464"; };
diff --git a/arch/mips/boot/dts/loongson/ls3-gs464e.dtsi b/arch/mips/boot/dts/loongson/ls3-gs464e.dtsi
new file mode 100644
index 000000000000..c5f545ef8d94
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/ls3-gs464e.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+
+&cpu0 { compatible = "loongson,gs464e"; };
+&cpu1 { compatible = "loongson,gs464e"; };
+&cpu2 { compatible = "loongson,gs464e"; };
+&cpu3 { compatible = "loongson,gs464e"; };
+&cpu4 { compatible = "loongson,gs464e"; };
+&cpu5 { compatible = "loongson,gs464e"; };
+&cpu6 { compatible = "loongson,gs464e"; };
+&cpu7 { compatible = "loongson,gs464e"; };
+&cpu8 { compatible = "loongson,gs464e"; };
+&cpu9 { compatible = "loongson,gs464e"; };
+&cpu10 { compatible = "loongson,gs464e"; };
+&cpu11 { compatible = "loongson,gs464e"; };
+&cpu12 { compatible = "loongson,gs464e"; };
+&cpu13 { compatible = "loongson,gs464e"; };
+&cpu14 { compatible = "loongson,gs464e"; };
+&cpu15 { compatible = "loongson,gs464e"; };
diff --git a/arch/mips/boot/dts/loongson/ls3-rs780e-pch.dtsi b/arch/mips/boot/dts/loongson/ls3-rs780e-pch.dtsi
new file mode 100644
index 000000000000..e971a44efc56
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/ls3-rs780e-pch.dtsi
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+ pch {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0x000 0x10000000 0x000 0x10000000 0x10000000
+ 0x000 0x40000000 0x000 0x40000000 0x40000000>;
+
+ isa {
+ compatible = "isa";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <1 0 0 0 0x1000>;
+
+ i8259: interrupt-controller@20 {
+ compatible = "intel,i8259";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ plat-poll;
+ interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
+ <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>;
+ interrupt-parent = <&htintc>;
+ };
+
+ rtc0: rtc@70 {
+ compatible = "motorola,mc146818";
+ reg = <1 0x70 0x8>;
+ interrupts = <8>;
+ interrupt-parent = <&i8259>;
+ };
+ };
+ };
+};
diff --git a/arch/mips/boot/dts/loongson/ls3a-package.dtsi b/arch/mips/boot/dts/loongson/ls3a-package.dtsi
new file mode 100644
index 000000000000..23e5c3a6a71e
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/ls3a-package.dtsi
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ package@0 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
+ 0 0x3ff00000 0 0x3ff00000 0x100000
+ 0xEFD 0xFB000000 0xEFD 0xFB000000 0x10000000 /* 3A HT Config Space */>;
+
+ iointc: interrupt-controller@3ff01400 {
+ compatible = "loongson,ls3-iointc";
+ reg = <0 0x3ff01400 0x64>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+
+ cpu_uart0: serial@1fe001e0 {
+ device_type = "serial";
+ compatible = "ns16550a";
+ reg = <0 0x1fe001e0 0x8>;
+ clock-frequency = <33000000>;
+ interrupt-parent = <&iointc>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+ no-loopback-test;
+ };
+
+ cpu_uart1: serial@1fe001e8 {
+ status = "disabled";
+ device_type = "serial";
+ compatible = "ns16550a";
+ reg = <0 0x1fe001e8 0x8>;
+ clock-frequency = <33000000>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&iointc>;
+ no-loopback-test;
+ };
+
+ htintc: interrupt-controller@0xEFDFB000080 {
+ compatible = "loongson,ls3-htintc";
+ reg = <0xEFD 0xFB000080 0x100>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&iointc>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
+ <25 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+};
diff --git a/arch/mips/boot/dts/loongson/ls3a1000_780e_1way.dts b/arch/mips/boot/dts/loongson/ls3a1000_780e_1way.dts
new file mode 100644
index 000000000000..6cf90d032cf6
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/ls3a1000_780e_1way.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "ls3-cpus.dtsi"
+#include "ls3-gs464.dtsi"
+#include "ls3a-package.dtsi"
+#include "ls3-rs780e-pch.dtsi"
+
+/ {
+ compatible = "loongson,ls3a1000-780e-1way";
+};
diff --git a/arch/mips/boot/dts/loongson/ls3a1000_780e_2way.dts b/arch/mips/boot/dts/loongson/ls3a1000_780e_2way.dts
new file mode 100644
index 000000000000..cb1325a2bd64
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/ls3a1000_780e_2way.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "ls3-cpus.dtsi"
+#include "ls3-gs464.dtsi"
+#include "ls3a-package.dtsi"
+#include "ls3-2nodes.dtsi"
+#include "ls3-rs780e-pch.dtsi"
+
+/ {
+ compatible = "loongson,ls3a1000-780e-2way";
+};
diff --git a/arch/mips/boot/dts/loongson/ls3a1000_780e_4way.dts b/arch/mips/boot/dts/loongson/ls3a1000_780e_4way.dts
new file mode 100644
index 000000000000..e6fa9859fa4f
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/ls3a1000_780e_4way.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "ls3-cpus.dtsi"
+#include "ls3-gs464.dtsi"
+#include "ls3a-package.dtsi"
+#include "ls3-4nodes.dtsi"
+#include "ls3-rs780e-pch.dtsi"
+
+/ {
+ compatible = "loongson,ls3a1000-780e-4way";
+};
diff --git a/arch/mips/boot/dts/loongson/ls3a2000_780e_1way.dts b/arch/mips/boot/dts/loongson/ls3a2000_780e_1way.dts
new file mode 100644
index 000000000000..a726f0186355
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/ls3a2000_780e_1way.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "ls3-cpus.dtsi"
+#include "ls3-gs464e.dtsi"
+#include "ls3a-package.dtsi"
+#include "ls3-rs780e-pch.dtsi"
+
+/ {
+ compatible = "loongson,ls3a2000-780e-1way";
+};
diff --git a/arch/mips/boot/dts/loongson/ls3a2000_780e_2way.dts b/arch/mips/boot/dts/loongson/ls3a2000_780e_2way.dts
new file mode 100644
index 000000000000..19268b640cae
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/ls3a2000_780e_2way.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "ls3-cpus.dtsi"
+#include "ls3-gs464e.dtsi"
+#include "ls3a-package.dtsi"
+#include "ls3-2nodes.dtsi"
+#include "ls3-rs780e-pch.dtsi"
+
+/ {
+ compatible = "loongson,ls3a2000-780e-2way";
+};
diff --git a/arch/mips/boot/dts/loongson/ls3a2000_780e_4way.dts b/arch/mips/boot/dts/loongson/ls3a2000_780e_4way.dts
new file mode 100644
index 000000000000..2b491396225b
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/ls3a2000_780e_4way.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "ls3-cpus.dtsi"
+#include "ls3-gs464e.dtsi"
+#include "ls3a-package.dtsi"
+#include "ls3-4nodes.dtsi"
+#include "ls3-rs780e-pch.dtsi"
+
+/ {
+ compatible = "loongson,ls3a2000-780e-4way";
+};
diff --git a/arch/mips/boot/dts/loongson/ls3a3000_780e_1way.dts b/arch/mips/boot/dts/loongson/ls3a3000_780e_1way.dts
new file mode 100644
index 000000000000..628c5d0a7a25
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/ls3a3000_780e_1way.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "ls3-cpus.dtsi"
+#include "ls3-gs464e.dtsi"
+#include "ls3a-package.dtsi"
+#include "ls3-rs780e-pch.dtsi"
+
+/ {
+ compatible = "loongson,ls3a3000-780e-1way";
+};
diff --git a/arch/mips/boot/dts/loongson/ls3a3000_780e_2way.dts b/arch/mips/boot/dts/loongson/ls3a3000_780e_2way.dts
new file mode 100644
index 000000000000..1390767ed462
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/ls3a3000_780e_2way.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "ls3-cpus.dtsi"
+#include "ls3-gs464e.dtsi"
+#include "ls3a-package.dtsi"
+#include "ls3-2nodes.dtsi"
+#include "ls3-rs780e-pch.dtsi"
+
+/ {
+ compatible = "loongson,ls3a3000-780e-2way";
+};
diff --git a/arch/mips/boot/dts/loongson/ls3a3000_780e_4way.dts b/arch/mips/boot/dts/loongson/ls3a3000_780e_4way.dts
new file mode 100644
index 000000000000..3f94c05e944a
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/ls3a3000_780e_4way.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "ls3-cpus.dtsi"
+#include "ls3-gs464e.dtsi"
+#include "ls3a-package.dtsi"
+#include "ls3-4nodes.dtsi"
+#include "ls3-rs780e-pch.dtsi"
+
+/ {
+ compatible = "loongson,ls3a3000-780e-4way";
+};
diff --git a/arch/mips/boot/dts/loongson/ls3b-package.dtsi b/arch/mips/boot/dts/loongson/ls3b-package.dtsi
new file mode 100644
index 000000000000..f7e71cd5ba5b
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/ls3b-package.dtsi
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ package@0 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
+ 0 0x3ff00000 0 0x3ff00000 0x100000
+ 0x1EFD 0xFB000000 0x1EFD 0xFB000000 0x10000000 /* 3B HT Config Space */>;
+
+ iointc: interrupt-controller@3ff01400 {
+ compatible = "loongson,ls3-iointc";
+ reg = <0 0x3ff01400 0x64>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+
+ cpu_uart0: serial@1fe001e0 {
+ device_type = "serial";
+ compatible = "ns16550a";
+ reg = <0 0x1fe001e0 0x8>;
+ clock-frequency = <33000000>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&iointc>;
+ no-loopback-test;
+ };
+
+ cpu_uart1: serial@1fe001e8 {
+ status = "disabled";
+ device_type = "serial";
+ compatible = "ns16550a";
+ reg = <0 0x1fe001e8 0x8>;
+ clock-frequency = <33000000>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&iointc>;
+ no-loopback-test;
+ };
+
+ htintc: interrupt-controller@0x1EFDFB000080 {
+ compatible = "loongson,ls3-htintc";
+ reg = <0x1EFD 0xFB000080 0x100>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&iointc>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
+ <25 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+};
diff --git a/arch/mips/boot/dts/loongson/ls3b_780e_1way.dts b/arch/mips/boot/dts/loongson/ls3b_780e_1way.dts
new file mode 100644
index 000000000000..9b73e0e49408
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/ls3b_780e_1way.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "ls3-cpus.dtsi"
+#include "ls3-gs464.dtsi"
+#include "ls3b-package.dtsi"
+#include "ls3-2nodes.dtsi" /* Yes, ls3b have 2 nodes per way */
+#include "ls3-rs780e-pch.dtsi"
+
+/ {
+ compatible = "loongson,ls3b-780e-1way";
+};
diff --git a/arch/mips/boot/dts/loongson/ls3b_780e_2way.dts b/arch/mips/boot/dts/loongson/ls3b_780e_2way.dts
new file mode 100644
index 000000000000..6090de8a32d3
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/ls3b_780e_2way.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "ls3-cpus.dtsi"
+#include "ls3-gs464.dtsi"
+#include "ls3b-package.dtsi"
+#include "ls3-4nodes.dtsi" /* Yes, ls3b have 2 nodes per way */
+#include "ls3-rs780e-pch.dtsi"
+
+/ {
+ compatible = "loongson,ls3b-780e-2way";
+};
--
2.22.0
next prev parent reply other threads:[~2019-08-27 8:55 UTC|newest]
Thread overview: 195+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-27 8:52 [PATCH 00/13] Modernize Loongson64 Machine Jiaxun Yang
2019-08-27 8:52 ` [PATCH 01/13] MIPS: Loongson64: Rename CPU TYPES Jiaxun Yang
2019-08-27 8:52 ` [PATCH 02/13] MIPS: Loongson64: Sepreate loongson2ef/loongson64 code Jiaxun Yang
2019-08-27 22:05 ` Aaro Koskinen
2019-08-28 0:37 ` Jiaxun Yang
2019-09-02 17:51 ` Aaro Koskinen
2019-08-27 8:52 ` [PATCH 03/13] MAINTAINERS: Fix entries for new loongson64 path Jiaxun Yang
2019-08-27 8:52 ` [PATCH 04/13] irqchip: Add driver for Loongson-3 I/O interrupt controller Jiaxun Yang
2019-08-27 16:45 ` Marc Zyngier
2019-08-28 0:27 ` Jiaxun Yang
2019-08-28 6:59 ` Marc Zyngier
2019-08-28 15:31 ` Jiaxun Yang
2019-08-28 16:02 ` Marc Zyngier
2019-08-27 8:52 ` [PATCH 05/13] dt-bindings: interrupt-controller: Add Loongson-3 IOINTC Jiaxun Yang
2019-08-27 13:08 ` Rob Herring
2019-08-27 8:52 ` [PATCH 06/13] irqchip: Add driver for Loongson-3 HyperTransport interrupt controller Jiaxun Yang
2019-08-27 12:53 ` Marc Zyngier
2019-08-27 8:52 ` [PATCH 07/13] dt-bindings: interrupt-controller: Add Loongson-3 HTINTC Jiaxun Yang
2019-08-27 12:49 ` Rob Herring
2019-08-27 14:08 ` Jiaxun Yang
2019-08-27 8:52 ` [PATCH 08/13] irqchip: i8259: Add plat-poll support Jiaxun Yang
2019-08-27 8:52 ` [PATCH 09/13] irqchip: mips-cpu: Convert to simple domain Jiaxun Yang
2019-08-27 8:52 ` [PATCH 10/13] MIPS: Loongson64: Drop legacy IRQ code Jiaxun Yang
2019-08-27 8:53 ` [PATCH 11/13] dt-bindings: mips: Add loongson cpus & boards Jiaxun Yang
2019-08-27 12:45 ` Rob Herring
2019-08-27 14:18 ` Jiaxun Yang
2019-08-27 20:41 ` Paul Burton
2019-08-28 0:15 ` Jiaxun Yang
2019-09-02 14:50 ` Rob Herring
2019-09-03 9:07 ` Paul Burton
2019-09-03 16:35 ` Jiaxun Yang
2019-09-04 3:33 ` Huacai Chen
2019-08-27 8:53 ` Jiaxun Yang [this message]
2019-08-27 8:53 ` [PATCH 13/13] MIPS: Loongson64: Load built-in dtbs Jiaxun Yang
2019-08-27 13:25 ` Re:[PATCH 00/13] Modernize Loongson64 Machine 陈华才
2019-08-27 13:25 ` 陈华才
2019-08-27 14:39 ` [PATCH " Jiaxun Yang
2019-08-30 4:25 ` [PATCH v1 00/18] " Jiaxun Yang
2019-08-30 4:25 ` [PATCH v1 01/18] MIPS: Loongson64: Rename CPU TYPES Jiaxun Yang
2019-08-30 4:25 ` [PATCH v1 02/18] MIPS: Loongson64: separate loongson2ef/loongson64 code Jiaxun Yang
2019-08-30 4:25 ` [PATCH v1 03/18] MAINTAINERS: Fix entries for new loongson64 path Jiaxun Yang
2019-08-30 4:25 ` [PATCH v1 04/18] irqchip: Export generic chip domain map/unmap functions Jiaxun Yang
2019-08-30 4:25 ` [PATCH v1 05/18] irqchip: Add driver for Loongson-3 I/O interrupt controller Jiaxun Yang
2019-08-30 4:25 ` [PATCH v1 06/18] dt-bindings: interrupt-controller: Add Loongson-3 IOINTC Jiaxun Yang
2019-09-05 14:42 ` [PATCH v2 00/19] Modernize Loongson64 Machine Jiaxun Yang
2019-09-05 14:42 ` [PATCH v2 01/19] MIPS: Loongson64: Rename CPU TYPES Jiaxun Yang
2019-09-05 14:42 ` [PATCH v2 02/19] MIPS: Loongson64: separate loongson2ef/loongson64 code Jiaxun Yang
2019-09-10 0:12 ` Paul Burton
2019-09-10 2:32 ` Jiaxun Yang
2019-09-16 2:23 ` Huacai Chen
2019-09-18 0:38 ` Jiaxun Yang
2019-09-05 14:43 ` [PATCH v2 03/19] MAINTAINERS: Fix entries for new loongson64 path Jiaxun Yang
2019-09-05 14:43 ` [PATCH v2 04/19] irqchip: Export generic chip domain map/unmap functions Jiaxun Yang
2019-09-05 14:43 ` [PATCH v2 05/19] irqchip: Add driver for Loongson-3 I/O interrupt controller Jiaxun Yang
2019-09-05 14:43 ` [PATCH v2 06/19] dt-bindings: interrupt-controller: Add Loongson-3 IOINTC Jiaxun Yang
2019-09-17 21:26 ` Rob Herring
2019-09-17 21:26 ` Rob Herring
2019-09-05 14:43 ` [PATCH v2 07/19] irqchip: Add driver for Loongson-3 HyperTransport interrupt controller Jiaxun Yang
2019-09-05 14:43 ` [PATCH v2 08/19] dt-bindings: interrupt-controller: Add Loongson-3 HTINTC Jiaxun Yang
2019-09-05 14:43 ` [PATCH v2 09/19] irqchip: i8259: Add plat-poll support Jiaxun Yang
2019-09-05 14:43 ` [PATCH v2 10/19] irqchip: mips-cpu: Convert to simple domain Jiaxun Yang
2019-09-05 14:43 ` [PATCH v2 11/19] MIPS: Loongson64: Drop legacy IRQ code Jiaxun Yang
2019-09-05 14:43 ` [PATCH v2 12/19] dt-bindings: mips: Add loongson boards Jiaxun Yang
2019-09-30 13:23 ` Rob Herring
2019-09-05 14:43 ` [PATCH v2 13/19] dt-bindings: Document loongson vendor-prefix Jiaxun Yang
2019-09-05 14:43 ` [PATCH v2 14/19] MIPS: Loongson64: Add generic dts Jiaxun Yang
2019-09-07 2:53 ` Huacai Chen
2019-09-07 3:14 ` Jiaxun Yang
2019-09-30 13:20 ` Rob Herring
2019-09-05 14:43 ` [PATCH v2 15/19] MIPS: Loongson64: Load built-in dtbs Jiaxun Yang
2019-09-05 14:43 ` [PATCH v2 16/19] GPIO: loongson: Drop Loongson-3A/3B support Jiaxun Yang
2019-09-05 14:43 ` [PATCH v2 17/19] MIPS: Loongson: Regenerate defconfigs Jiaxun Yang
2019-09-05 14:43 ` [PATCH v2 18/19] MAINTAINERS: Add new pathes to LOONGSON64 ARCHITECTURE Jiaxun Yang
2019-09-05 14:43 ` [PATCH v2 19/19] MAINTAINERS: Add myself as maintainer of LOONGSON64 Jiaxun Yang
2019-09-07 3:13 ` [PATCH v2 00/19] Modernize Loongson64 Machine Huacai Chen
2019-09-12 6:30 ` [PATCH 00/13] " Matt Turner
2019-09-18 0:33 ` Jiaxun Yang
2020-01-12 8:14 ` [PATCH v3 00/10] " Jiaxun Yang
2020-01-12 8:14 ` [PATCH v3 01/10] dt-bindings: Document loongson vendor-prefix Jiaxun Yang
2020-01-15 18:59 ` Paul Burton
2020-01-12 8:14 ` [PATCH v3 02/10] irqchip: Add driver for Loongson I/O interrupt controller Jiaxun Yang
2020-01-12 8:14 ` [PATCH v3 03/10] dt-bindings: interrupt-controller: Add Loongson IOINTC Jiaxun Yang
2020-01-13 3:44 ` Huacai Chen
2020-01-13 3:40 ` Jiaxun Yang
2020-01-12 8:14 ` [PATCH v3 04/10] irqchip: Add driver for Loongson-3 HyperTransport PIC controller Jiaxun Yang
2020-01-12 8:14 ` [PATCH v3 05/10] dt-bindings: interrupt-controller: Add Loongson-3 HTPIC Jiaxun Yang
2020-01-12 8:14 ` [PATCH v3 06/10] irqchip: mips-cpu: Convert to simple domain Jiaxun Yang
2020-01-12 8:14 ` [PATCH v3 07/10] MIPS: Loongson64: Drop legacy IRQ code Jiaxun Yang
2020-01-12 8:14 ` [PATCH v3 08/10] dt-bindings: mips: Add loongson boards Jiaxun Yang
2020-01-13 3:39 ` Huacai Chen
2020-01-12 8:14 ` [PATCH v3 09/10] MIPS: Loongson64: Add generic dts Jiaxun Yang
2020-01-12 8:14 ` [PATCH v3 10/10] MIPS: Loongson64: Load built-in dtbs Jiaxun Yang
2020-01-13 3:38 ` [PATCH v3 00/10] Modernize Loongson64 Machine Huacai Chen
2020-02-21 5:09 ` [PATCH v4 00/10] Modernize Loongson64 Machine v4 Jiaxun Yang
2020-02-21 5:09 ` [PATCH v4 01/10] irqchip: Add driver for Loongson I/O Local Interrupt Controller Jiaxun Yang
2020-02-29 2:30 ` 回复:[PATCH " Jiaxun Yang
2020-03-07 14:50 ` [PATCH " Marc Zyngier
2020-02-21 5:09 ` [PATCH v4 02/10] dt-bindings: interrupt-controller: Add Loongson LIOINTC Jiaxun Yang
2020-02-21 5:09 ` [PATCH v4 03/10] irqchip: Add driver for Loongson-3 HyperTransport PIC controller Jiaxun Yang
2020-03-07 15:01 ` Marc Zyngier
2020-02-21 5:09 ` [PATCH v4 04/10] dt-bindings: interrupt-controller: Add Loongson-3 HTPIC Jiaxun Yang
2020-02-21 5:09 ` [PATCH v4 05/10] irqchip: mips-cpu: Convert to simple domain Jiaxun Yang
2020-02-21 5:09 ` [PATCH v4 06/10] MIPS: Loongson64: Drop legacy IRQ code Jiaxun Yang
2020-02-21 5:09 ` [PATCH v4 07/10] dt-bindings: mips: Add loongson boards Jiaxun Yang
2020-02-26 16:52 ` Rob Herring
2020-02-29 2:28 ` Jiaxun Yang
2020-02-21 5:09 ` [PATCH v4 08/10] MIPS: Loongson64: Add generic dts Jiaxun Yang
2020-02-21 5:09 ` [PATCH v4 09/10] MIPS: Loongson64: Load built-in dtbs Jiaxun Yang
2020-02-21 5:09 ` [PATCH v4 10/10] MIPS: Loongson64: Move MIPS_CPU_IRQ_BASE Jiaxun Yang
2020-03-18 6:20 ` [PATCH v5 00/11] Modernize Loongson64 Machine v5 Jiaxun Yang
2020-03-18 6:20 ` [PATCH v5 01/11] irqchip: Add driver for Loongson I/O Local Interrupt Controller Jiaxun Yang
2020-03-18 6:20 ` [PATCH v5 02/11] irqchip: loongson-liointc: Workaround LPC IRQ Errata Jiaxun Yang
2020-03-18 6:20 ` [PATCH v5 03/11] dt-bindings: interrupt-controller: Add Loongson LIOINTC Jiaxun Yang
2020-03-18 6:20 ` [PATCH v5 04/11] irqchip: Add driver for Loongson-3 HyperTransport PIC controller Jiaxun Yang
2020-03-21 14:14 ` Marc Zyngier
2020-03-18 6:20 ` [PATCH v5 05/11] dt-bindings: interrupt-controller: Add Loongson-3 HTPIC Jiaxun Yang
2020-03-18 6:20 ` [PATCH v5 06/11] irqchip: mips-cpu: Convert to simple domain Jiaxun Yang
2020-03-18 6:20 ` [PATCH v5 07/11] MIPS: Loongson64: Drop legacy IRQ code Jiaxun Yang
2020-03-18 6:20 ` [PATCH v5 08/11] dt-bindings: mips: Add loongson boards Jiaxun Yang
2020-03-20 22:36 ` Rob Herring
2020-03-22 5:33 ` Zhou Yanjie
2020-03-18 6:20 ` [PATCH v5 09/11] MIPS: Loongson64: Add generic dts Jiaxun Yang
2020-03-18 6:20 ` [PATCH v5 10/11] MIPS: Loongson64: Load built-in dtbs Jiaxun Yang
2020-03-18 6:20 ` [PATCH v5 11/11] MIPS: Loongson64: Move MIPS_CPU_IRQ_BASE Jiaxun Yang
2020-03-24 15:35 ` [PATCH v6 00/11] Modernize Loongson64 Machine v6 Jiaxun Yang
2020-03-24 15:35 ` [PATCH v6 01/11] irqchip: Add driver for Loongson I/O Local Interrupt Controller Jiaxun Yang
2020-03-24 15:35 ` [PATCH v6 02/11] irqchip: loongson-liointc: Workaround LPC IRQ Errata Jiaxun Yang
2020-03-25 1:52 ` Huacai Chen
2020-03-25 2:31 ` Jiaxun Yang
2020-03-24 15:36 ` [PATCH v6 03/11] dt-bindings: interrupt-controller: Add Loongson LIOINTC Jiaxun Yang
2020-03-24 15:36 ` [PATCH v6 04/11] irqchip: Add driver for Loongson-3 HyperTransport PIC controller Jiaxun Yang
2020-03-24 15:36 ` [PATCH v6 05/11] dt-bindings: interrupt-controller: Add Loongson-3 HTPIC Jiaxun Yang
2020-03-24 15:36 ` [PATCH v6 06/11] irqchip: mips-cpu: Convert to simple domain Jiaxun Yang
2020-03-24 15:36 ` [PATCH v6 07/11] MIPS: Loongson64: Drop legacy IRQ code Jiaxun Yang
2020-03-24 15:36 ` [PATCH v6 08/11] dt-bindings: mips: Add loongson boards Jiaxun Yang
2020-03-24 15:36 ` [PATCH v6 09/11] MIPS: Loongson64: Add generic dts Jiaxun Yang
2020-03-25 2:11 ` Huacai Chen
2020-03-25 2:08 ` Jiaxun Yang
2020-03-25 2:49 ` Huacai Chen
2020-03-24 15:36 ` [PATCH v6 10/11] MIPS: Loongson64: Load built-in dtbs Jiaxun Yang
2020-03-24 15:36 ` [PATCH v6 11/11] MIPS: Loongson64: Move MIPS_CPU_IRQ_BASE Jiaxun Yang
2020-03-24 15:47 ` [PATCH v6 00/11] Modernize Loongson64 Machine v6 Marc Zyngier
2020-03-24 15:51 ` Jiaxun Yang
2020-03-24 18:07 ` Thomas Bogendoerfer
2020-03-25 2:28 ` [PATCH v7 00/12] " Jiaxun Yang
2020-03-25 2:28 ` Jiaxun Yang
2020-03-25 2:28 ` Jiaxun Yang
2020-03-25 2:28 ` [PATCH v7 01/12] irqchip: Add driver for Loongson I/O Local Interrupt Controller Jiaxun Yang
2020-03-25 2:28 ` Jiaxun Yang
2020-03-25 2:28 ` Jiaxun Yang
2020-03-25 11:25 ` Paul Cercueil
2020-03-25 11:25 ` Paul Cercueil
2020-03-25 11:25 ` Paul Cercueil
2020-03-25 11:35 ` Marc Zyngier
2020-03-25 11:35 ` Marc Zyngier
2020-03-25 11:35 ` Marc Zyngier
2020-03-25 2:28 ` [PATCH v7 01/12] MIPS: Loongson: Do not initialise statics to 0 Jiaxun Yang
2020-03-25 2:28 ` Jiaxun Yang
2020-03-25 2:28 ` Jiaxun Yang
2020-03-25 2:28 ` [PATCH v7 02/12] irqchip: loongson-liointc: Workaround LPC IRQ Errata Jiaxun Yang
2020-03-25 2:28 ` Jiaxun Yang
2020-03-25 2:28 ` Jiaxun Yang
2020-03-25 2:28 ` [PATCH v7 02/12] MIPS: DTS: CI20: add DT node for IR sensor Jiaxun Yang
2020-03-25 2:28 ` Jiaxun Yang
2020-03-25 2:28 ` Jiaxun Yang
2020-03-25 2:28 ` [PATCH v7 03/12] dt-bindings: interrupt-controller: Add Loongson LIOINTC Jiaxun Yang
2020-03-25 2:28 ` Jiaxun Yang
2020-03-25 2:28 ` Jiaxun Yang
2020-03-25 3:54 ` [PATCH v8 00/11] Modernize Loongson64 Machine v8 Jiaxun Yang
2020-03-25 3:54 ` [PATCH v8 01/11] irqchip: Add driver for Loongson I/O Local Interrupt Controller Jiaxun Yang
2020-03-25 3:54 ` [PATCH v8 02/11] irqchip: loongson-liointc: Workaround LPC IRQ Errata Jiaxun Yang
2020-03-25 3:54 ` [PATCH v8 03/11] dt-bindings: interrupt-controller: Add Loongson LIOINTC Jiaxun Yang
2020-03-25 3:54 ` [PATCH v8 04/11] irqchip: Add driver for Loongson-3 HyperTransport PIC controller Jiaxun Yang
2020-03-25 3:54 ` [PATCH v8 05/11] dt-bindings: interrupt-controller: Add Loongson-3 HTPIC Jiaxun Yang
2020-03-25 3:54 ` [PATCH v8 06/11] irqchip: mips-cpu: Convert to simple domain Jiaxun Yang
2020-03-25 12:37 ` Thomas Bogendoerfer
2020-03-25 12:48 ` Jiaxun Yang
2020-03-25 13:00 ` Marc Zyngier
2020-03-25 13:07 ` Jiaxun Yang
2020-03-25 13:57 ` Marc Zyngier
2020-03-25 13:59 ` Jiaxun Yang
2020-03-25 14:15 ` Marc Zyngier
2020-03-25 14:31 ` Jiaxun Yang
2020-03-25 15:02 ` Marc Zyngier
2020-03-25 15:04 ` Thomas Bogendoerfer
2020-03-25 15:09 ` Jiaxun Yang
2020-03-25 15:46 ` Thomas Bogendoerfer
2020-03-25 16:02 ` Jiaxun Yang
2020-03-25 16:31 ` Thomas Bogendoerfer
2020-03-25 3:55 ` [PATCH v8 07/11] MIPS: Loongson64: Drop legacy IRQ code Jiaxun Yang
2020-03-25 3:55 ` [PATCH v8 08/11] dt-bindings: mips: Add loongson boards Jiaxun Yang
2020-03-25 3:55 ` [PATCH v8 09/11] MIPS: Loongson64: Add generic dts Jiaxun Yang
2020-03-25 3:55 ` [PATCH v8 10/11] MIPS: Loongson64: Load built-in dtbs Jiaxun Yang
2020-03-25 3:55 ` [PATCH v8 11/11] MAINTAINERS: Update Loongson64 entry Jiaxun Yang
2020-03-25 17:33 ` [PATCH v8 00/11] Modernize Loongson64 Machine v8 Thomas Bogendoerfer
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