From: Jitao Shi <jitao.shi@mediatek.com>
To: CK Hu <ck.hu@mediatek.com>, David Airlie <airlied@linux.ie>,
Daniel Vetter <daniel@ffwll.ch>,
dri-devel@lists.freedesktop.org
Cc: Jitao Shi <jitao.shi@mediatek.com>,
srv_heupstream@mediatek.com, stonea168@163.com,
cawa.cheng@mediatek.com, sj.huang@mediatek.com,
linux-mediatek@lists.infradead.org,
Matthias Brugger <matthias.bgg@gmail.com>,
yingjoe.chen@mediatek.com, eddie.huang@mediatek.com
Subject: [PATCH v7 4/9] drm/mediatek: add dsi reg commit disable control
Date: Thu, 19 Sep 2019 14:58:01 +0800 [thread overview]
Message-ID: <20190919065806.111016-5-jitao.shi@mediatek.com> (raw)
In-Reply-To: <20190919065806.111016-1-jitao.shi@mediatek.com>
New DSI IP has shadow register and working reg. The register
values are writen to shadow register. And then trigger with
commit reg, the register values will be moved working register.
This fucntion is defualt on. But this driver doesn't use this
function. So add the disable control.
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index ac8e80e379f7..314bfb1c827b 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -123,6 +123,10 @@
#define VM_CMD_EN BIT(0)
#define TS_VFP_EN BIT(5)
+#define DSI_SHADOW_DEBUG 0x190U
+#define FORCE_COMMIT BIT(0)
+#define BYPASS_SHADOW BIT(1)
+
#define CONFIG (0xff << 0)
#define SHORT_PACKET 0
#define LONG_PACKET 2
@@ -149,6 +153,7 @@ struct phy;
struct mtk_dsi_driver_data {
const u32 reg_cmdq_off;
+ bool has_shadow_ctl;
};
struct mtk_dsi {
@@ -586,6 +591,11 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
}
mtk_dsi_enable(dsi);
+
+ if (dsi->driver_data->has_shadow_ctl)
+ writel(FORCE_COMMIT | BYPASS_SHADOW,
+ dsi->regs + DSI_SHADOW_DEBUG);
+
mtk_dsi_reset_engine(dsi);
mtk_dsi_phy_timconfig(dsi);
--
2.21.0
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next prev parent reply other threads:[~2019-09-19 6:58 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-19 6:57 [PATCH v7 0/9] Support dsi for mt8183 Jitao Shi
2019-09-19 6:57 ` [PATCH v7 1/9] drm/mediatek: move mipi_dsi_host_register to probe Jitao Shi
2019-09-19 6:57 ` [PATCH v7 2/9] drm/mediatek: fixes CMDQ reg address of mt8173 is different with mt2701 Jitao Shi
2019-09-26 8:50 ` CK Hu
2019-09-19 6:58 ` [PATCH v7 3/9] drm/mediatek: replace writeb() with mtk_dsi_mask() Jitao Shi
2019-09-26 8:50 ` CK Hu
2019-09-19 6:58 ` Jitao Shi [this message]
2019-09-19 6:58 ` [PATCH v7 5/9] drm/mediatek: add frame size control Jitao Shi
2019-09-19 6:58 ` [PATCH v7 6/9] drm/mediatek: add mt8183 dsi driver support Jitao Shi
2019-09-19 6:58 ` [PATCH v7 7/9] drm/mediatek: change the dsi phytiming calculate method Jitao Shi
2019-09-26 8:51 ` CK Hu
2019-12-12 13:53 ` Enric Balletbo Serra
2019-12-12 13:53 ` Enric Balletbo Serra
2019-12-12 22:47 ` Ryan Case
2019-12-12 22:47 ` Ryan Case
2019-12-13 2:45 ` CK Hu
2019-12-13 2:45 ` CK Hu
2019-09-19 6:58 ` [PATCH v7 8/9] drm: mediatek: adjust dsi and mipi_tx probe sequence Jitao Shi
2019-09-19 6:58 ` [PATCH v7 9/9] drm/mediatek: add dphy reset after setting lanes number Jitao Shi
2019-09-26 8:52 ` CK Hu
2019-09-27 1:35 ` [PATCH v7 0/9] Support dsi for mt8183 CK Hu
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