From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 5/5] drm/i915/display/cnl+: Handle fused off DSC
Date: Fri, 18 Oct 2019 17:41:24 -0700 [thread overview]
Message-ID: <20191019004124.371929-5-jose.souza@intel.com> (raw)
In-Reply-To: <20191019004124.371929-1-jose.souza@intel.com>
DSC could be fused off, so not all GEN10+ platforms will support it.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Martin Peres <martin.peres@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_device_info.c | 4 ++++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
5 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3792d143bea9..e01690701fdd 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1888,6 +1888,9 @@ static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ if (!INTEL_INFO(dev_priv)->display.has_dsc)
+ return false;
+
/* On TGL, DSC is supported on all Pipes */
if (INTEL_GEN(dev_priv) >= 12)
return true;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f2280709c8c9..09dbfea7c81f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -737,6 +737,7 @@ static const struct intel_device_info intel_coffeelake_gt3_info = {
GEN9_FEATURES, \
GEN(10), \
.ddb_size = 1024, \
+ .display.has_dsc = 1, \
.has_coherent_ggtt = false, \
GLK_COLORS
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 84fca4f3af5a..bfa301759b6c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7665,6 +7665,7 @@ enum {
#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
#define TGL_DFSM_PIPE_D_DISABLE (1 << 22)
+#define CNL_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
#define SKL_DSSM _MMIO(0x51004)
#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 97d962944e48..6a24e85c6d10 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -996,6 +996,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
info->display.has_csr = 0;
+
+ if (INTEL_GEN(dev_priv) >= 10 &&
+ (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
+ info->display.has_dsc = 0;
}
/* Initialize slice/subslice/EU info */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 118d922261e2..ba31d68bb7ba 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -136,6 +136,7 @@ enum intel_ppgtt_type {
func(has_ddi); \
func(has_dp_mst); \
func(has_dsb); \
+ func(has_dsc); \
func(has_fbc); \
func(has_gmch); \
func(has_hdcp); \
--
2.23.0
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next prev parent reply other threads:[~2019-10-19 0:41 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-19 0:41 [PATCH 1/5] drm/i915/display: Handle fused off display correctly José Roberto de Souza
2019-10-19 0:41 ` [PATCH 2/5] drm/i915/display: Handle fused off HDCP José Roberto de Souza
2019-10-23 13:37 ` Ramalingam C
2019-10-23 13:37 ` [Intel-gfx] " Ramalingam C
2019-10-23 18:54 ` Souza, Jose
2019-10-23 18:54 ` [Intel-gfx] " Souza, Jose
2019-10-24 6:57 ` Ramalingam C
2019-10-24 6:57 ` [Intel-gfx] " Ramalingam C
2019-10-19 0:41 ` [PATCH 3/5] drm/i915/display: Check if FBC is fused off José Roberto de Souza
2019-10-23 13:50 ` Ramalingam C
2019-10-23 13:50 ` [Intel-gfx] " Ramalingam C
2019-10-19 0:41 ` [PATCH 4/5] drm/i915/display/icl+: Check if DMC " José Roberto de Souza
2019-10-24 7:06 ` Ramalingam C
2019-10-24 7:06 ` [Intel-gfx] " Ramalingam C
2019-10-19 0:41 ` José Roberto de Souza [this message]
2019-10-23 18:37 ` [PATCH 5/5] drm/i915/display/cnl+: Handle fused off DSC Manasi Navare
2019-10-23 18:37 ` [Intel-gfx] " Manasi Navare
2019-10-24 6:55 ` Ramalingam C
2019-10-24 6:55 ` [Intel-gfx] " Ramalingam C
2019-10-19 1:34 ` ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915/display: Handle fused off display correctly Patchwork
2019-10-19 4:15 ` ✓ Fi.CI.IGT: " Patchwork
2019-10-23 12:15 ` [PATCH 1/5] " Jani Nikula
2019-10-23 12:15 ` [Intel-gfx] " Jani Nikula
2019-10-23 13:18 ` Ramalingam C
2019-10-23 13:18 ` [Intel-gfx] " Ramalingam C
2019-10-23 13:23 ` Jani Nikula
2019-10-23 13:23 ` [Intel-gfx] " Jani Nikula
2019-10-23 19:13 ` Souza, Jose
2019-10-23 19:13 ` [Intel-gfx] " Souza, Jose
2019-10-23 13:43 ` Ramalingam C
2019-10-23 13:43 ` [Intel-gfx] " Ramalingam C
2019-10-26 0:13 [PATCH 1/5] drm/i915: Add two spaces before the SKL_DFSM registers José Roberto de Souza
2019-10-26 0:13 ` [PATCH 5/5] drm/i915/display/cnl+: Handle fused off DSC José Roberto de Souza
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