From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
Viresh Kumar <viresh.kumar@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Peter Geis <pgwipeout@gmail.com>,
Nicolas Chauvet <kwizart@gmail.com>,
Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v4 09/10] ARM: dts: tegra30: beaver: Set up voltage regulators for DVFS
Date: Mon, 11 Nov 2019 23:54:18 +0300 [thread overview]
Message-ID: <20191111205419.16768-10-digetx@gmail.com> (raw)
In-Reply-To: <20191111205419.16768-1-digetx@gmail.com>
Set min/max voltage and couple CPU/CORE regulators.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/boot/dts/tegra30-beaver.dts | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index a3b0f3555cd2..6ebb3105af9e 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -1806,9 +1806,14 @@
vddctrl_reg: vddctrl {
regulator-name = "vdd_cpu,vdd_sys";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-coupled-with = <&core_vdd_reg>;
+ regulator-coupled-max-spread = <300000>;
+ regulator-max-step-microvolt = <100000>;
regulator-always-on;
+
+ nvidia,tegra-cpu-regulator;
};
vio_reg: vio {
@@ -1868,17 +1873,22 @@
};
};
- tps62361@60 {
+ core_vdd_reg: tps62361@60 {
compatible = "ti,tps62361";
reg = <0x60>;
regulator-name = "tps62361-vout";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1500000>;
+ regulator-coupled-with = <&vddctrl_reg>;
+ regulator-coupled-max-spread = <300000>;
+ regulator-max-step-microvolt = <100000>;
regulator-boot-on;
regulator-always-on;
ti,vsel0-state-high;
ti,vsel1-state-high;
+
+ nvidia,tegra-core-regulator;
};
};
--
2.23.0
next prev parent reply other threads:[~2019-11-11 20:54 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-11 20:54 [PATCH v4 00/10] NVIDIA Tegra20 CPUFreq driver major update Dmitry Osipenko
2019-11-11 20:54 ` [PATCH v4 01/10] clk: tegra: Add custom CCLK implementation Dmitry Osipenko
2019-11-11 20:54 ` [PATCH v4 02/10] clk: tegra: pll: Add pre/post rate-change hooks Dmitry Osipenko
2019-11-11 20:54 ` [PATCH v4 03/10] clk: tegra: cclk: Add helpers for handling PLLX rate changes Dmitry Osipenko
2019-11-11 20:54 ` [PATCH v4 04/10] clk: tegra20: Use custom CCLK implementation Dmitry Osipenko
2019-11-11 20:54 ` [PATCH v4 05/10] clk: tegra30: " Dmitry Osipenko
2019-11-11 20:54 ` [PATCH v4 06/10] dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30 Dmitry Osipenko
2019-11-11 20:54 ` [PATCH v4 07/10] cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported now) Dmitry Osipenko
2019-11-11 20:54 ` [PATCH v4 08/10] ARM: tegra: Create tegra20-cpufreq platform device on Tegra30 Dmitry Osipenko
2019-11-11 20:54 ` Dmitry Osipenko [this message]
2019-11-11 20:54 ` [PATCH v4 10/10] ARM: dts: tegra30: beaver: Add CPU Operating Performance Points Dmitry Osipenko
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