From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, Stafford Horne <shorne@gmail.com>
Subject: [PULL 1/1] target/openrisc: Fix FPCSR mask to allow setting DZF
Date: Thu, 16 Jan 2020 14:54:40 -1000 [thread overview]
Message-ID: <20200117005440.3524-2-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200117005440.3524-1-richard.henderson@linaro.org>
From: Stafford Horne <shorne@gmail.com>
The mask used when setting FPCSR allows setting bits 10 to 1. However,
OpenRISC has flags and config bits in 11 to 1, 11 being Divide by Zero
Flag (DZF). This seems like an off-by-one bug.
This was found when testing the GLIBC test suite which has test cases to
set and clear all bits.
Signed-off-by: Stafford Horne <shorne@gmail.com>
Message-Id: <20200110212843.27335-1-shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/openrisc/fpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c
index 59e1413279..6f75ea0505 100644
--- a/target/openrisc/fpu_helper.c
+++ b/target/openrisc/fpu_helper.c
@@ -70,7 +70,7 @@ void cpu_set_fpcsr(CPUOpenRISCState *env, uint32_t val)
float_round_down
};
- env->fpcsr = val & 0x7ff;
+ env->fpcsr = val & 0xfff;
set_float_rounding_mode(rm_to_sf[extract32(val, 1, 2)], &env->fp_status);
}
--
2.20.1
next prev parent reply other threads:[~2020-01-17 0:55 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-17 0:54 [PULL 0/1] target/openrisc patch queue Richard Henderson
2020-01-17 0:54 ` Richard Henderson [this message]
2020-01-17 14:55 ` Peter Maydell
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