From: Thierry Reding <thierry.reding@gmail.com>
To: Vidya Sagar <vidyas@nvidia.com>
Cc: bhelgaas@google.com, lorenzo.pieralisi@arm.com,
rjw@rjwysocki.net, lenb@kernel.org, andrew.murray@arm.com,
treding@nvidia.com, jonathanh@nvidia.com,
linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org,
linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org,
kthota@nvidia.com, mmaddireddy@nvidia.com, sagar.tv@gmail.com
Subject: Re: [PATCH V3 2/2] PCI: Add MCFG quirks for Tegra194 host controllers
Date: Fri, 17 Jan 2020 12:42:47 +0100 [thread overview]
Message-ID: <20200117114247.GA166525@ulmo> (raw)
In-Reply-To: <20200110191500.9538-3-vidyas@nvidia.com>
[-- Attachment #1: Type: text/plain, Size: 1578 bytes --]
On Sat, Jan 11, 2020 at 12:45:00AM +0530, Vidya Sagar wrote:
> The PCIe controller in Tegra194 SoC is not completely ECAM-compliant.
> With the current hardware design limitations in place, ECAM can be enabled
> only for one controller (C5 controller to be precise) with bus numbers
> starting from 160 instead of 0. A different approach is taken to avoid this
> abnormal way of enabling ECAM for just one controller but to enable
> configuration space access for all the other controllers. In this approach,
> ops are added through MCFG quirk mechanism which access the configuration
> spaces by dynamically programming iATU (internal AddressTranslation Unit)
> to generate respective configuration accesses just like the way it is
> done in DesignWare core sub-system.
>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> Reported-by: kbuild test robot <lkp@intel.com>
> ---
> V3:
> * Removed MCFG address hardcoding in pci_mcfg.c file
> * Started using 'dbi_base' for accessing root port's own config space
> * and using 'config_base' for accessing config space of downstream hierarchy
>
> V2:
> * Fixed build issues reported by kbuild test bot
>
> drivers/acpi/pci_mcfg.c | 7 ++
> drivers/pci/controller/dwc/Kconfig | 3 +-
> drivers/pci/controller/dwc/Makefile | 2 +-
> drivers/pci/controller/dwc/pcie-tegra194.c | 102 +++++++++++++++++++++
> include/linux/pci-ecam.h | 1 +
> 5 files changed, 113 insertions(+), 2 deletions(-)
Acked-by: Thierry Reding <treding@nvidia.com>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
next prev parent reply other threads:[~2020-01-17 11:42 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-03 17:49 [PATCH] PCI: Add MCFG quirks for Tegra194 host controllers Vidya Sagar
2020-01-03 17:49 ` Vidya Sagar
2020-01-03 18:04 ` Bjorn Helgaas
2020-01-04 3:44 ` Vidya Sagar
2020-01-04 3:44 ` Vidya Sagar
2020-01-17 12:17 ` Lorenzo Pieralisi
2020-01-20 11:10 ` Thierry Reding
2020-01-20 15:18 ` Lorenzo Pieralisi
2020-01-20 15:18 ` Lorenzo Pieralisi
[not found] ` <20200120151849.GA24402-LhTu/34fCX3ZROr8t4l/smS4ubULX0JqMm0uRHvK7Nw@public.gmane.org>
2020-01-21 13:44 ` Thierry Reding
2020-01-21 13:44 ` Thierry Reding
2020-01-23 10:49 ` Lorenzo Pieralisi
2020-01-23 10:49 ` Lorenzo Pieralisi
2020-02-06 16:46 ` Thierry Reding
2020-02-07 14:50 ` Bjorn Helgaas
2020-02-07 16:51 ` Thierry Reding
2020-02-07 18:34 ` Bjorn Helgaas
2020-01-04 21:53 ` kbuild test robot
2020-01-04 21:53 ` kbuild test robot
2020-01-04 21:53 ` kbuild test robot
2020-01-06 8:27 ` [PATCH V2] " Vidya Sagar
2020-01-06 8:27 ` Vidya Sagar
[not found] ` <20200106082709.14370-1-vidyas-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2020-01-10 19:14 ` [PATCH V3 0/2] " Vidya Sagar
2020-01-10 19:14 ` Vidya Sagar
[not found] ` <20200110191500.9538-1-vidyas-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2020-01-10 19:14 ` [PATCH V3 1/2] arm64: tegra: Re-order PCIe aperture mappings to support ACPI boot Vidya Sagar
2020-01-10 19:14 ` Vidya Sagar
2020-06-29 13:31 ` Jon Hunter
2020-06-29 13:31 ` Jon Hunter
2020-06-30 10:52 ` Vidya Sagar
2020-06-30 10:52 ` Vidya Sagar
2020-01-10 19:15 ` [PATCH V3 2/2] PCI: Add MCFG quirks for Tegra194 host controllers Vidya Sagar
2020-01-10 19:15 ` Vidya Sagar
2020-01-17 11:42 ` Thierry Reding [this message]
2021-03-05 21:57 ` Bjorn Helgaas
2021-03-05 23:04 ` Krzysztof Wilczyński
2021-04-16 13:45 ` Vidya Sagar
2021-04-16 13:45 ` [PATCH V4] " Vidya Sagar
2021-04-16 19:06 ` Bjorn Helgaas
2021-05-13 9:40 ` [PATCH V3 2/2] " Qu Wenruo
2021-05-13 13:05 ` Vidya Sagar
2020-01-16 17:18 ` [PATCH V3 0/2] " Vidya Sagar
2020-01-16 17:18 ` Vidya Sagar
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200117114247.GA166525@ulmo \
--to=thierry.reding@gmail.com \
--cc=andrew.murray@arm.com \
--cc=bhelgaas@google.com \
--cc=jonathanh@nvidia.com \
--cc=kthota@nvidia.com \
--cc=lenb@kernel.org \
--cc=linux-acpi@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=mmaddireddy@nvidia.com \
--cc=rjw@rjwysocki.net \
--cc=sagar.tv@gmail.com \
--cc=treding@nvidia.com \
--cc=vidyas@nvidia.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.