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From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org
Cc: lvivier@redhat.com, "Thomas Huth" <thuth@redhat.com>,
	qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org,
	"Cédric Le Goater" <clg@kaod.org>,
	"David Gibson" <david@gibson.dropbear.id.au>
Subject: [PULL 21/34] ppc/pnv: change the PowerNV machine devices to be non user creatable
Date: Fri, 31 Jan 2020 17:09:11 +1100	[thread overview]
Message-ID: <20200131060924.147449-22-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <20200131060924.147449-1-david@gibson.dropbear.id.au>

From: Cédric Le Goater <clg@kaod.org>

The PowerNV machine emulates an OpenPOWER system and the PowerNV chip
devices are models of the internal logic of the POWER processor. They
can not be instantiated by the user on the QEMU command line.

The PHB3/PHB4 devices could be an exception in the future after some
rework on how the device tree is built. For the moment, exclude them
also.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20200129113720.7404-1-clg@kaod.org>
Tested-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
 hw/pci-host/pnv_phb3.c      | 2 ++
 hw/pci-host/pnv_phb3_pbcq.c | 1 +
 hw/pci-host/pnv_phb4.c      | 3 ++-
 hw/pci-host/pnv_phb4_pec.c  | 2 ++
 hw/ppc/pnv_core.c           | 2 ++
 hw/ppc/pnv_homer.c          | 1 +
 hw/ppc/pnv_lpc.c            | 1 +
 hw/ppc/pnv_occ.c            | 1 +
 8 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c
index f03399c406..74618fadf0 100644
--- a/hw/pci-host/pnv_phb3.c
+++ b/hw/pci-host/pnv_phb3.c
@@ -1115,6 +1115,7 @@ static void pnv_phb3_class_init(ObjectClass *klass, void *data)
     dc->realize = pnv_phb3_realize;
     device_class_set_props(dc, pnv_phb3_properties);
     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
+    dc->user_creatable = false;
 }
 
 static const TypeInfo pnv_phb3_type_info = {
@@ -1168,6 +1169,7 @@ static void pnv_phb3_root_port_class_init(ObjectClass *klass, void *data)
 
     device_class_set_parent_realize(dc, pnv_phb3_root_port_realize,
                                     &rpc->parent_realize);
+    dc->user_creatable = false;
 
     k->vendor_id = PCI_VENDOR_ID_IBM;
     k->device_id = 0x03dc;
diff --git a/hw/pci-host/pnv_phb3_pbcq.c b/hw/pci-host/pnv_phb3_pbcq.c
index 6f0c05be68..f232228b0e 100644
--- a/hw/pci-host/pnv_phb3_pbcq.c
+++ b/hw/pci-host/pnv_phb3_pbcq.c
@@ -335,6 +335,7 @@ static void pnv_pbcq_class_init(ObjectClass *klass, void *data)
     xdc->dt_xscom = pnv_pbcq_dt_xscom;
 
     dc->realize = pnv_pbcq_realize;
+    dc->user_creatable = false;
 }
 
 static const TypeInfo pnv_pbcq_type_info = {
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index 61235d13a6..23cf093928 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -1290,7 +1290,7 @@ static void pnv_phb4_class_init(ObjectClass *klass, void *data)
     dc->realize         = pnv_phb4_realize;
     device_class_set_props(dc, pnv_phb4_properties);
     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
-    dc->user_creatable  = true;
+    dc->user_creatable  = false;
     dc->reset           = pnv_phb4_reset;
 
     xfc->notify         = pnv_phb4_xive_notify;
@@ -1368,6 +1368,7 @@ static void pnv_phb4_root_port_class_init(ObjectClass *klass, void *data)
     PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
 
     dc->desc     = "IBM PHB4 PCIE Root Port";
+    dc->user_creatable = false;
 
     device_class_set_parent_realize(dc, pnv_phb4_root_port_realize,
                                     &rpc->parent_realize);
diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c
index fd92041d69..68e1db3eac 100644
--- a/hw/pci-host/pnv_phb4_pec.c
+++ b/hw/pci-host/pnv_phb4_pec.c
@@ -490,6 +490,7 @@ static void pnv_pec_class_init(ObjectClass *klass, void *data)
 
     dc->realize = pnv_pec_realize;
     device_class_set_props(dc, pnv_pec_properties);
+    dc->user_creatable = false;
 
     pecc->xscom_nest_base = pnv_pec_xscom_nest_base;
     pecc->xscom_pci_base  = pnv_pec_xscom_pci_base;
@@ -568,6 +569,7 @@ static void pnv_pec_stk_class_init(ObjectClass *klass, void *data)
 
     device_class_set_props(dc, pnv_pec_stk_properties);
     dc->realize = pnv_pec_stk_realize;
+    dc->user_creatable = false;
 
     /* TODO: reset regs ? */
 }
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index f7247222bc..234562040d 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -325,6 +325,7 @@ static void pnv_core_class_init(ObjectClass *oc, void *data)
     dc->realize = pnv_core_realize;
     dc->unrealize = pnv_core_unrealize;
     device_class_set_props(dc, pnv_core_properties);
+    dc->user_creatable = false;
 }
 
 #define DEFINE_PNV_CORE_TYPE(family, cpu_model) \
@@ -423,6 +424,7 @@ static void pnv_quad_class_init(ObjectClass *oc, void *data)
 
     dc->realize = pnv_quad_realize;
     device_class_set_props(dc, pnv_quad_properties);
+    dc->user_creatable = false;
 }
 
 static const TypeInfo pnv_quad_info = {
diff --git a/hw/ppc/pnv_homer.c b/hw/ppc/pnv_homer.c
index 93ae42f7e4..9a262629b7 100644
--- a/hw/ppc/pnv_homer.c
+++ b/hw/ppc/pnv_homer.c
@@ -360,6 +360,7 @@ static void pnv_homer_class_init(ObjectClass *klass, void *data)
     dc->realize = pnv_homer_realize;
     dc->desc = "PowerNV HOMER Memory";
     device_class_set_props(dc, pnv_homer_properties);
+    dc->user_creatable = false;
 }
 
 static const TypeInfo pnv_homer_type_info = {
diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
index d1de98f04c..5989d723c5 100644
--- a/hw/ppc/pnv_lpc.c
+++ b/hw/ppc/pnv_lpc.c
@@ -762,6 +762,7 @@ static void pnv_lpc_class_init(ObjectClass *klass, void *data)
     dc->realize = pnv_lpc_realize;
     dc->desc = "PowerNV LPC Controller";
     device_class_set_props(dc, pnv_lpc_properties);
+    dc->user_creatable = false;
 }
 
 static const TypeInfo pnv_lpc_info = {
diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c
index 2173fac0e7..5a716c256e 100644
--- a/hw/ppc/pnv_occ.c
+++ b/hw/ppc/pnv_occ.c
@@ -280,6 +280,7 @@ static void pnv_occ_class_init(ObjectClass *klass, void *data)
     dc->realize = pnv_occ_realize;
     dc->desc = "PowerNV OCC Controller";
     device_class_set_props(dc, pnv_occ_properties);
+    dc->user_creatable = false;
 }
 
 static const TypeInfo pnv_occ_type_info = {
-- 
2.24.1



  parent reply	other threads:[~2020-01-31  6:17 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-31  6:08 [PULL 00/34] ppc-for-5.0 queue 20200131 David Gibson
2020-01-31  6:08 ` [PULL 01/34] ppc/pnv: use QEMU unit definition MiB David Gibson
2020-01-31  6:08 ` [PULL 02/34] ppc/pnv: improve error logging when a PNOR update fails David Gibson
2020-01-31  6:08 ` [PULL 03/34] ppc:virtex_ml507: remove unused arguments David Gibson
2020-01-31  6:08 ` [PULL 04/34] hw/ppc/prep: Remove the deprecated "prep" machine and the OpenHackware BIOS David Gibson
2020-01-31  6:08 ` [PULL 05/34] target/ppc: Clarify the meaning of return values in kvm_handle_debug David Gibson
2020-01-31  6:08 ` [PULL 06/34] spapr: Fail CAS if option vector table cannot be parsed David Gibson
2020-01-31  6:08 ` [PULL 07/34] target/ppc: Add privileged message send facilities David Gibson
2020-01-31  6:08 ` [PULL 08/34] target/ppc: add support for Hypervisor Facility Unavailable Exception David Gibson
2020-01-31  6:08 ` [PULL 09/34] spapr: Don't allow multiple active vCPUs at CAS David Gibson
2020-01-31  6:09 ` [PULL 10/34] ppc/pnv: Add support for HRMOR on Radix host David Gibson
2020-01-31  6:09 ` [PULL 11/34] ppc/pnv: remove useless "core-pir" property alias David Gibson
2020-01-31  6:09 ` [PULL 12/34] ppc/pnv: Add support for "hostboot" mode David Gibson
2020-01-31  6:09 ` [PULL 13/34] tpm: Move tpm_tis_show_buffer to tpm_util.c David Gibson
2020-01-31  6:09 ` [PULL 14/34] spapr: Implement get_dt_compatible() callback David Gibson
2020-01-31  6:09 ` [PULL 15/34] tpm_spapr: Support TPM for ppc64 using CRQ based interface David Gibson
2020-01-31  6:09 ` [PULL 16/34] tpm_spapr: Support suspend and resume David Gibson
2020-01-31  6:09 ` [PULL 17/34] hw/ppc/Kconfig: Enable TPM_SPAPR as part of PSERIES config David Gibson
2020-01-31  6:09 ` [PULL 18/34] docs/specs/tpm: reST-ify TPM documentation David Gibson
2020-01-31  6:09 ` [PULL 19/34] ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge David Gibson
2020-01-31  6:09 ` [PULL 20/34] ppc/pnv: Add models for POWER8 PHB3 " David Gibson
2020-01-31  6:09 ` David Gibson [this message]
2020-01-31  6:09 ` [PULL 22/34] spapr: Enable DD2.3 accelerated count cache flush in pseries-5.0 machine David Gibson
2020-01-31  6:09 ` [PULL 23/34] target/ppc/cpu.h: Put macro parameter in parentheses David Gibson
2020-01-31  6:09 ` [PULL 24/34] Wrapper function to wait on condition for the main loop mutex David Gibson
2020-01-31  6:09 ` [PULL 25/34] ppc: spapr: Introduce FWNMI capability David Gibson
2020-01-31  6:09 ` [PULL 26/34] target/ppc: Handle NMI guest exit David Gibson
2020-01-31  6:09 ` [PULL 27/34] target/ppc: Build rtas error log upon an MCE David Gibson
2020-01-31  6:09 ` [PULL 28/34] ppc: spapr: Handle "ibm, nmi-register" and "ibm, nmi-interlock" RTAS calls David Gibson
2020-01-31  6:09 ` [PULL 29/34] migration: Include migration support for machine check handling David Gibson
2020-01-31  6:09 ` [PULL 30/34] ppc: spapr: Activate the FWNMI functionality David Gibson
2020-01-31  6:09 ` [PULL 31/34] target/ppc: Use probe_access for LSW, STSW David Gibson
2020-01-31  6:09 ` [PULL 32/34] target/ppc: Use probe_access for LMW, STMW David Gibson
2020-01-31  6:09 ` [PULL 33/34] target/ppc: Remove redundant mask in DCBZ David Gibson
2020-01-31  6:09 ` [PULL 34/34] target/ppc: Use probe_write for DCBZ David Gibson
2020-01-31 16:42 ` [PULL 00/34] ppc-for-5.0 queue 20200131 Peter Maydell
2020-02-02  8:43   ` David Gibson
2020-02-02 10:33     ` Greg Kurz

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