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From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 10/12] drm/i915: Flush idle barriers when waiting
Date: Fri, 31 Jan 2020 10:45:46 +0000	[thread overview]
Message-ID: <20200131104548.2451485-10-chris@chris-wilson.co.uk> (raw)
In-Reply-To: <20200131104548.2451485-1-chris@chris-wilson.co.uk>

If we do find ourselves with an idle barrier inside our active while
waiting, attempt to flush it by emitting a pulse using the kernel
context.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Steve Carbonari <steven.carbonari@intel.com>
---
 drivers/gpu/drm/i915/i915_active.c           | 42 ++++++++++++++----
 drivers/gpu/drm/i915/selftests/i915_active.c | 46 ++++++++++++++++++++
 2 files changed, 79 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_active.c b/drivers/gpu/drm/i915/i915_active.c
index da58e5d084f4..3074d6c2b7cc 100644
--- a/drivers/gpu/drm/i915/i915_active.c
+++ b/drivers/gpu/drm/i915/i915_active.c
@@ -7,6 +7,7 @@
 #include <linux/debugobjects.h>
 
 #include "gt/intel_context.h"
+#include "gt/intel_engine_heartbeat.h"
 #include "gt/intel_engine_pm.h"
 #include "gt/intel_ring.h"
 
@@ -456,26 +457,49 @@ static void enable_signaling(struct i915_active_fence *active)
 	dma_fence_put(fence);
 }
 
-int i915_active_wait(struct i915_active *ref)
+static int flush_barrier(struct active_node *it)
 {
-	struct active_node *it, *n;
-	int err = 0;
+	struct intel_engine_cs *engine;
 
-	might_sleep();
+	if (!is_barrier(&it->base))
+		return 0;
 
-	if (!i915_active_acquire_if_busy(ref))
+	engine = __barrier_to_engine(it);
+	smp_rmb(); /* serialise with add_active_barriers */
+	if (!is_barrier(&it->base))
 		return 0;
 
-	/* Flush lazy signals */
+	return intel_engine_flush_barriers(engine);
+}
+
+static int flush_lazy_signals(struct i915_active *ref)
+{
+	struct active_node *it, *n;
+	int err = 0;
+
 	enable_signaling(&ref->excl);
 	rbtree_postorder_for_each_entry_safe(it, n, &ref->tree, node) {
-		if (is_barrier(&it->base)) /* unconnected idle barrier */
-			continue;
+		err = flush_barrier(it); /* unconnected idle barrier? */
+		if (err)
+			break;
 
 		enable_signaling(&it->base);
 	}
-	/* Any fence added after the wait begins will not be auto-signaled */
 
+	return err;
+}
+
+int i915_active_wait(struct i915_active *ref)
+{
+	int err;
+
+	might_sleep();
+
+	if (!i915_active_acquire_if_busy(ref))
+		return 0;
+
+	/* Any fence added after the wait begins will not be auto-signaled */
+	err = flush_lazy_signals(ref);
 	i915_active_release(ref);
 	if (err)
 		return err;
diff --git a/drivers/gpu/drm/i915/selftests/i915_active.c b/drivers/gpu/drm/i915/selftests/i915_active.c
index ef572a0c2566..067e30b8927f 100644
--- a/drivers/gpu/drm/i915/selftests/i915_active.c
+++ b/drivers/gpu/drm/i915/selftests/i915_active.c
@@ -201,11 +201,57 @@ static int live_active_retire(void *arg)
 	return err;
 }
 
+static int live_active_barrier(void *arg)
+{
+	struct drm_i915_private *i915 = arg;
+	struct intel_engine_cs *engine;
+	struct live_active *active;
+	int err = 0;
+
+	/* Check that we get a callback when requests retire upon waiting */
+
+	active = __live_alloc(i915);
+	if (!active)
+		return -ENOMEM;
+
+	err = i915_active_acquire(&active->base);
+	if (err)
+		goto out;
+
+	for_each_uabi_engine(engine, i915) {
+		err = i915_active_acquire_preallocate_barrier(&active->base,
+							      engine);
+		if (err)
+			break;
+
+		i915_active_acquire_barrier(&active->base);
+	}
+
+	i915_active_release(&active->base);
+
+	if (err == 0)
+		err = i915_active_wait(&active->base);
+
+	if (err == 0 && !READ_ONCE(active->retired)) {
+		pr_err("i915_active not retired after flushing barriers!\n");
+		err = -EINVAL;
+	}
+
+out:
+	__live_put(active);
+
+	if (igt_flush_test(i915))
+		err = -EIO;
+
+	return err;
+}
+
 int i915_active_live_selftests(struct drm_i915_private *i915)
 {
 	static const struct i915_subtest tests[] = {
 		SUBTEST(live_active_wait),
 		SUBTEST(live_active_retire),
+		SUBTEST(live_active_barrier),
 	};
 
 	if (intel_gt_is_wedged(&i915->gt))
-- 
2.25.0

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  parent reply	other threads:[~2020-01-31 10:46 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-31 10:45 [Intel-gfx] [PATCH 01/12] drm/i915/gem: Require per-engine reset support for non-persistent contexts Chris Wilson
2020-01-31 10:45 ` [Intel-gfx] [PATCH 02/12] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt Chris Wilson
2020-01-31 10:45 ` [Intel-gfx] [PATCH 03/12] drm/i915/selftests: Also wait for the scratch buffer to be bound Chris Wilson
2020-01-31 10:45 ` [Intel-gfx] [PATCH 04/12] drm/i915/gt: Yield the timeslice if caught waiting on a user semaphore Chris Wilson
2020-01-31 10:45 ` [Intel-gfx] [PATCH 05/12] drm/i915/gvt: Use the pinned ce->lrc_reg_state Chris Wilson
2020-01-31 10:45 ` [Intel-gfx] [PATCH 06/12] drm/i915/gt: Pull sseu context updates under gt Chris Wilson
2020-02-03 15:41   ` Matthew Auld
2020-01-31 10:45 ` [Intel-gfx] [PATCH 07/12] drm/i915/gt: Move move context layout registers and offsets to lrc_reg.h Chris Wilson
2020-01-31 10:45 ` [Intel-gfx] [PATCH 08/12] drm/i915/gt: Rename lrc.c to execlists_submission.c Chris Wilson
2020-01-31 18:55   ` Daniele Ceraolo Spurio
2020-03-25 18:32     ` Daniele Ceraolo Spurio
2020-01-31 10:45 ` [Intel-gfx] [PATCH 09/12] drm/i915/gt: Split logical ring context manipulation into intel_lrc.c Chris Wilson
2020-01-31 10:45 ` Chris Wilson [this message]
2020-01-31 10:45 ` [Intel-gfx] [PATCH 11/12] drm/i915: Allow userspace to specify ringsize on construction Chris Wilson
2020-01-31 10:45 ` [Intel-gfx] [PATCH 12/12] drm/i915/gem: Honour O_NONBLOCK before throttling execbuf submissions Chris Wilson
2020-01-31 13:49 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/12] drm/i915/gem: Require per-engine reset support for non-persistent contexts Patchwork
2020-01-31 14:35 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-02-03 14:54 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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