From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Warn about the hidden i915_vma_pin in timeline_get_seqno
Date: Fri, 31 Jan 2020 20:24:03 +0000 [thread overview]
Message-ID: <20200131202403.3429558-2-chris@chris-wilson.co.uk> (raw)
In-Reply-To: <20200131202403.3429558-1-chris@chris-wilson.co.uk>
On seqno rollover, we need to allocate ourselves a new cacheline. This
might incur grabbing a new page and pinning it into the GGTT, with some
rather unfortunate lockdep implications.
To avoid a mutex, and more specifically pinning in the GGTT from inside
the kernel context being used to flush the GGTT in emergencies, we will
likely need to lift the next-cacheline allocation to a pre-reservation.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_timeline.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c
index 465f87b65901..54e1e55f3c81 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -406,6 +406,8 @@ __intel_timeline_get_seqno(struct intel_timeline *tl,
void *vaddr;
int err;
+ might_lock(&tl->gt->ggtt->vm.mutex);
+
/*
* If there is an outstanding GPU reference to this cacheline,
* such as it being sampled by a HW semaphore on another timeline,
--
2.25.0
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next prev parent reply other threads:[~2020-01-31 20:24 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-31 20:24 [Intel-gfx] [PATCH 1/2] drm/i915: Initialise basic fence before acquiring seqno Chris Wilson
2020-01-31 20:24 ` Chris Wilson [this message]
2020-01-31 23:49 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] " Patchwork
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