From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 07/33] target/arm: Add isar_feature_aa32_vfp_simd
Date: Fri, 28 Feb 2020 16:38:14 +0000 [thread overview]
Message-ID: <20200228163840.23585-8-peter.maydell@linaro.org> (raw)
In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org>
From: Richard Henderson <richard.henderson@linaro.org>
Use this in the places that were checking ARM_FEATURE_VFP, and
are obviously testing for the existance of the register set
as opposed to testing for some particular instruction extension.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200224222232.13807-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 9 +++++++++
hw/intc/armv7m_nvic.c | 20 ++++++++++----------
linux-user/arm/signal.c | 4 ++--
target/arm/arch_dump.c | 11 ++++++-----
target/arm/cpu.c | 4 ++--
target/arm/helper.c | 4 ++--
target/arm/m_helper.c | 11 ++++++-----
7 files changed, 37 insertions(+), 26 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 65171cb30ee..a128d48d405 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3450,6 +3450,15 @@ static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
}
+static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id)
+{
+ /*
+ * Return true if either VFP or SIMD is implemented.
+ * In this case, a minimum of VFP w/ D0-D15.
+ */
+ return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0;
+}
+
static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id)
{
/* Return true if D16-D31 are implemented */
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 22a43e49847..a62587eb3f0 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -1262,12 +1262,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
case 0xd84: /* CSSELR */
return cpu->env.v7m.csselr[attrs.secure];
case 0xd88: /* CPACR */
- if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
return 0;
}
return cpu->env.v7m.cpacr[attrs.secure];
case 0xd8c: /* NSACR */
- if (!attrs.secure || !arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (!attrs.secure || !cpu_isar_feature(aa32_vfp_simd, cpu)) {
return 0;
}
return cpu->env.v7m.nsacr;
@@ -1417,7 +1417,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
}
return cpu->env.v7m.sfar;
case 0xf34: /* FPCCR */
- if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
return 0;
}
if (attrs.secure) {
@@ -1444,12 +1444,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
return value;
}
case 0xf38: /* FPCAR */
- if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
return 0;
}
return cpu->env.v7m.fpcar[attrs.secure];
case 0xf3c: /* FPDSCR */
- if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
return 0;
}
return cpu->env.v7m.fpdscr[attrs.secure];
@@ -1711,13 +1711,13 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
}
break;
case 0xd88: /* CPACR */
- if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
/* We implement only the Floating Point extension's CP10/CP11 */
cpu->env.v7m.cpacr[attrs.secure] = value & (0xf << 20);
}
break;
case 0xd8c: /* NSACR */
- if (attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (attrs.secure && cpu_isar_feature(aa32_vfp_simd, cpu)) {
/* We implement only the Floating Point extension's CP10/CP11 */
cpu->env.v7m.nsacr = value & (3 << 10);
}
@@ -1951,7 +1951,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
break;
}
case 0xf34: /* FPCCR */
- if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
/* Not all bits here are banked. */
uint32_t fpccr_s;
@@ -2005,13 +2005,13 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
}
break;
case 0xf38: /* FPCAR */
- if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
value &= ~7;
cpu->env.v7m.fpcar[attrs.secure] = value;
}
break;
case 0xf3c: /* FPDSCR */
- if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
value &= 0x07c00000;
cpu->env.v7m.fpdscr[attrs.secure] = value;
}
diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c
index b0e753801b6..d96fc27ce11 100644
--- a/linux-user/arm/signal.c
+++ b/linux-user/arm/signal.c
@@ -346,7 +346,7 @@ static void setup_sigframe_v2(struct target_ucontext_v2 *uc,
setup_sigcontext(&uc->tuc_mcontext, env, set->sig[0]);
/* Save coprocessor signal frame. */
regspace = uc->tuc_regspace;
- if (arm_feature(env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {
regspace = setup_sigframe_v2_vfp(regspace, env);
}
if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
@@ -671,7 +671,7 @@ static int do_sigframe_return_v2(CPUARMState *env,
/* Restore coprocessor signal frame */
regspace = uc->tuc_regspace;
- if (arm_feature(env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {
regspace = restore_sigframe_v2_vfp(env, regspace);
if (!regspace) {
return 1;
diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c
index 2345dec3c2c..7693e17e964 100644
--- a/target/arm/arch_dump.c
+++ b/target/arm/arch_dump.c
@@ -363,9 +363,11 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
int cpuid, void *opaque)
{
struct arm_note note;
- CPUARMState *env = &ARM_CPU(cs)->env;
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
DumpState *s = opaque;
- int ret, i, fpvalid = !!arm_feature(env, ARM_FEATURE_VFP);
+ int ret, i;
+ bool fpvalid = cpu_isar_feature(aa32_vfp_simd, cpu);
arm_note_init(¬e, s, "CORE", 5, NT_PRSTATUS, sizeof(note.prstatus));
@@ -444,7 +446,6 @@ int cpu_get_dump_info(ArchDumpInfo *info,
ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)
{
ARMCPU *cpu = ARM_CPU(first_cpu);
- CPUARMState *env = &cpu->env;
size_t note_size;
if (class == ELFCLASS64) {
@@ -452,12 +453,12 @@ ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)
note_size += AARCH64_PRFPREG_NOTE_SIZE;
#ifdef TARGET_AARCH64
if (cpu_isar_feature(aa64_sve, cpu)) {
- note_size += AARCH64_SVE_NOTE_SIZE(env);
+ note_size += AARCH64_SVE_NOTE_SIZE(&cpu->env);
}
#endif
} else {
note_size = ARM_PRSTATUS_NOTE_SIZE;
- if (arm_feature(env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
note_size += ARM_VFP_NOTE_SIZE;
}
}
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 2eadf4dcb8b..be4c2a1253d 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -293,7 +293,7 @@ static void arm_cpu_reset(CPUState *s)
env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK;
}
- if (arm_feature(env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK;
env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK |
R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK;
@@ -1011,7 +1011,7 @@ static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
int numvfpregs = 0;
if (cpu_isar_feature(aa32_simd_r32, cpu)) {
numvfpregs = 32;
- } else if (arm_feature(env, ARM_FEATURE_VFP)) {
+ } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
numvfpregs = 16;
}
for (i = 0; i < numvfpregs; i++) {
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 79db169e046..8841cc7fde8 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -894,7 +894,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
* ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
* TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
*/
- if (arm_feature(env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {
/* VFP coprocessor: cp10 & cp11 [23:20] */
mask |= (1 << 31) | (1 << 30) | (0xf << 20);
@@ -7814,7 +7814,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
} else if (cpu_isar_feature(aa32_simd_r32, cpu)) {
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
35, "arm-vfp3.xml", 0);
- } else if (arm_feature(env, ARM_FEATURE_VFP)) {
+ } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
19, "arm-vfp.xml", 0);
}
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index 33d414a684b..5e8a795d202 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -738,7 +738,8 @@ static uint32_t v7m_integrity_sig(CPUARMState *env, uint32_t lr)
*/
uint32_t sig = 0xfefa125a;
- if (!arm_feature(env, ARM_FEATURE_VFP) || (lr & R_V7M_EXCRET_FTYPE_MASK)) {
+ if (!cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))
+ || (lr & R_V7M_EXCRET_FTYPE_MASK)) {
sig |= 1;
}
return sig;
@@ -841,7 +842,7 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
if (dotailchain) {
/* Sanitize LR FType and PREFIX bits */
- if (!arm_feature(env, ARM_FEATURE_VFP)) {
+ if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
lr |= R_V7M_EXCRET_FTYPE_MASK;
}
lr = deposit32(lr, 24, 8, 0xff);
@@ -1373,7 +1374,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu)
ftype = excret & R_V7M_EXCRET_FTYPE_MASK;
- if (!arm_feature(env, ARM_FEATURE_VFP) && !ftype) {
+ if (!ftype && !cpu_isar_feature(aa32_vfp_simd, cpu)) {
qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero FTYPE in exception "
"exit PC value 0x%" PRIx32 " is UNPREDICTABLE "
"if FPU not present\n",
@@ -2450,7 +2451,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
* SFPA is RAZ/WI from NS. FPCA is RO if NSACR.CP10 == 0,
* RES0 if the FPU is not present, and is stored in the S bank
*/
- if (arm_feature(env, ARM_FEATURE_VFP) &&
+ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env)) &&
extract32(env->v7m.nsacr, 10, 1)) {
env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_FPCA_MASK;
env->v7m.control[M_REG_S] |= val & R_V7M_CONTROL_FPCA_MASK;
@@ -2565,7 +2566,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
env->v7m.control[env->v7m.secure] &= ~R_V7M_CONTROL_NPRIV_MASK;
env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK;
}
- if (arm_feature(env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {
/*
* SFPA is RAZ/WI from NS or if no FPU.
* FPCA is RO if NSACR.CP10 == 0, RES0 if the FPU is not present.
--
2.20.1
next prev parent reply other threads:[~2020-02-28 16:41 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
2020-02-28 16:38 ` [PULL 01/33] hw/arm: Use TYPE_PL011 to create serial port Peter Maydell
2020-02-28 16:38 ` [PULL 02/33] target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn Peter Maydell
2020-02-28 16:38 ` [PULL 03/33] hw/arm/integratorcp: Map the audio codec controller Peter Maydell
2020-02-28 16:38 ` [PULL 04/33] arm_gic: Mask the un-supported priority bits Peter Maydell
2020-02-28 16:38 ` [PULL 05/33] cpu/a9mpcore: Set number of GIC priority bits to 5 Peter Maydell
2020-02-28 16:38 ` [PULL 06/33] cpu/arm11mpcore: Set number of GIC priority bits to 4 Peter Maydell
2020-02-28 16:38 ` Peter Maydell [this message]
2020-02-28 16:38 ` [PULL 08/33] target/arm: Rename isar_feature_aa32_fpdp_v2 Peter Maydell
2020-02-28 16:38 ` [PULL 09/33] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3} Peter Maydell
2020-02-28 16:38 ` [PULL 10/33] target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfp Peter Maydell
2020-02-28 16:38 ` [PULL 11/33] target/arm: Perform fpdp_v2 check first Peter Maydell
2020-02-28 16:38 ` [PULL 12/33] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3 Peter Maydell
2020-02-28 16:38 ` [PULL 13/33] target/arm: Add missing checks for fpsp_v2 Peter Maydell
2020-02-28 16:38 ` [PULL 14/33] target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac Peter Maydell
2020-02-28 16:38 ` [PULL 15/33] target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn Peter Maydell
2020-02-28 16:38 ` [PULL 16/33] target/arm: Move VLLDM and VLSTM to vfp.decode Peter Maydell
2020-02-28 16:38 ` [PULL 17/33] target/arm: Move the vfp decodetree calls next to the base isa Peter Maydell
2020-02-28 16:38 ` [PULL 18/33] linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAP Peter Maydell
2020-02-28 16:38 ` [PULL 19/33] target/arm: Remove ARM_FEATURE_VFP* Peter Maydell
2020-02-28 16:38 ` [PULL 20/33] target/arm: Add formats for some vfp 2 and 3-register insns Peter Maydell
2020-02-28 16:38 ` [PULL 21/33] target/arm: Split VFM decode Peter Maydell
2020-02-28 16:38 ` [PULL 22/33] target/arm: Split VMINMAXNM decode Peter Maydell
2020-02-28 16:38 ` [PULL 23/33] hw/arm/xilinx_zynq: Fix USB port instantiation Peter Maydell
2021-05-19 17:50 ` Philippe Mathieu-Daudé
2020-02-28 16:38 ` [PULL 24/33] hw/usb/hcd-ehci-sysbus: Remove obsolete xlnx, ps7-usb class Peter Maydell
2020-02-28 16:38 ` [PULL 25/33] tests/acceptance: Add a test for the N800 and N810 arm machines Peter Maydell
2020-10-17 17:51 ` Philippe Mathieu-Daudé
2020-10-19 6:31 ` Thomas Huth
2020-10-19 9:30 ` Philippe Mathieu-Daudé
2020-10-19 9:43 ` Philippe Mathieu-Daudé
2020-10-23 15:43 ` Igor Mammedov
2020-10-23 17:39 ` Philippe Mathieu-Daudé
2020-10-23 19:04 ` Igor Mammedov
2020-10-25 17:03 ` Peter Maydell
2020-10-26 13:36 ` Igor Mammedov
2020-10-26 14:26 ` Peter Maydell
2020-10-27 10:54 ` Igor Mammedov
2020-02-28 16:38 ` [PULL 26/33] tests/acceptance: Add a test for the integratorcp arm machine Peter Maydell
2020-02-28 16:38 ` [PULL 27/33] tests/acceptance: Extract boot_integratorcp() from test_integratorcp() Peter Maydell
2020-02-28 16:38 ` [PULL 28/33] tests/acceptance/integratorcp: Verify Tux is displayed on framebuffer Peter Maydell
2020-02-28 16:38 ` [PULL 29/33] target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0 Peter Maydell
2020-02-28 16:38 ` [PULL 30/33] target/arm: Implement v8.3-RCPC Peter Maydell
2020-02-28 16:38 ` [PULL 31/33] target/arm: Implement v8.4-RCPC Peter Maydell
2020-02-28 16:38 ` [PULL 32/33] target/arm: Implement ARMv8.3-CCIDX Peter Maydell
2020-02-28 16:38 ` [PULL 33/33] hw/intc/arm_gic_kvm: Don't assume kernel can provide a GICv2 Peter Maydell
2020-02-28 17:59 ` [PULL 00/33] target-arm queue Peter Maydell
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