From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: qemu-devel@nongnu.org
Cc: damien.hedde@greensocs.com, peter.maydell@linaro.org,
sstabellini@kernel.org, edgar.iglesias@xilinx.com,
sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com,
jasowang@redhat.com, alistair@alistair23.me,
frederic.konrad@adacore.com, qemu-arm@nongnu.org,
philmd@redhat.com, luc.michel@greensocs.com, figlesia@xilinx.com
Subject: [PATCH v1 1/9] hw/net/xilinx_axienet: Auto-clear PHY Autoneg
Date: Thu, 30 Apr 2020 18:24:31 +0200 [thread overview]
Message-ID: <20200430162439.2659-2-edgar.iglesias@gmail.com> (raw)
In-Reply-To: <20200430162439.2659-1-edgar.iglesias@gmail.com>
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Auto-clear PHY CR Autoneg bits. This makes this model
work with recent Linux kernels.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
hw/net/xilinx_axienet.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
index 704788811a..0f97510d8a 100644
--- a/hw/net/xilinx_axienet.c
+++ b/hw/net/xilinx_axienet.c
@@ -149,8 +149,8 @@ tdk_write(struct PHY *phy, unsigned int req, unsigned int data)
break;
}
- /* Unconditionally clear regs[BMCR][BMCR_RESET] */
- phy->regs[0] &= ~0x8000;
+ /* Unconditionally clear regs[BMCR][BMCR_RESET] and auto-neg */
+ phy->regs[0] &= ~0x8200;
}
static void
--
2.20.1
next prev parent reply other threads:[~2020-04-30 16:29 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-30 16:24 [PATCH v1 0/9] hw/core: stream: Add end-of-packet flag Edgar E. Iglesias
2020-04-30 16:24 ` Edgar E. Iglesias [this message]
2020-05-04 15:29 ` [PATCH v1 1/9] hw/net/xilinx_axienet: Auto-clear PHY Autoneg Francisco Iglesias
2020-04-30 16:24 ` [PATCH v1 2/9] hw/net/xilinx_axienet: Cleanup stream->push assignment Edgar E. Iglesias
2020-05-04 15:29 ` Francisco Iglesias
2020-05-05 16:30 ` Alistair Francis
2020-04-30 16:24 ` [PATCH v1 3/9] hw/net/xilinx_axienet: Remove unncessary cast Edgar E. Iglesias
2020-05-04 15:30 ` Francisco Iglesias
2020-05-05 16:30 ` Alistair Francis
2020-04-30 16:24 ` [PATCH v1 4/9] hw/dma/xilinx_axidma: Add DMA memory-region property Edgar E. Iglesias
2020-05-04 15:30 ` Francisco Iglesias
2020-05-05 16:32 ` Alistair Francis
2020-04-30 16:24 ` [PATCH v1 5/9] hw/core: stream: Add an end-of-packet flag Edgar E. Iglesias
2020-05-05 14:20 ` Francisco Iglesias
2020-05-05 16:35 ` Alistair Francis
2020-04-30 16:24 ` [PATCH v1 6/9] hw/net/xilinx_axienet: Handle fragmented packets from DMA Edgar E. Iglesias
2020-05-05 14:20 ` Francisco Iglesias
2020-05-05 14:52 ` Edgar E. Iglesias
2020-04-30 16:24 ` [PATCH v1 7/9] hw/dma/xilinx_axidma: mm2s: Stream descriptor by descriptor Edgar E. Iglesias
2020-05-05 19:57 ` Alistair Francis
2020-04-30 16:24 ` [PATCH v1 8/9] hw/dma/xilinx_axidma: s2mm: Support stream fragments Edgar E. Iglesias
2020-05-05 19:59 ` Alistair Francis
2020-04-30 16:24 ` [PATCH v1 9/9] MAINTAINERS: Add myself as streams maintainer Edgar E. Iglesias
2020-05-05 19:57 ` Alistair Francis
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