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From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: gregkh@linuxfoundation.org
Cc: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 22/23] coresight: cti: Add CPU Hotplug handling to CTI driver
Date: Mon, 18 May 2020 12:02:41 -0600	[thread overview]
Message-ID: <20200518180242.7916-23-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <20200518180242.7916-1-mathieu.poirier@linaro.org>

From: Mike Leach <mike.leach@linaro.org>

Adds registration of CPU start and stop functions to CPU hotplug
mechanisms - for any CPU bound CTI.

Sets CTI powered flag according to state.
Will enable CTI on CPU start if there are existing enable requests.

Signed-off-by: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/hwtracing/coresight/coresight-cti.c | 92 +++++++++++++++++++++
 include/linux/cpuhotplug.h                  |  1 +
 2 files changed, 93 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-cti.c b/drivers/hwtracing/coresight/coresight-cti.c
index be61c1705916..7e7ec6dd93c0 100644
--- a/drivers/hwtracing/coresight/coresight-cti.c
+++ b/drivers/hwtracing/coresight/coresight-cti.c
@@ -8,6 +8,7 @@
 #include <linux/atomic.h>
 #include <linux/bits.h>
 #include <linux/coresight.h>
+#include <linux/cpuhotplug.h>
 #include <linux/device.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
@@ -40,6 +41,12 @@ static DEFINE_MUTEX(ect_mutex);
 #define csdev_to_cti_drvdata(csdev)	\
 	dev_get_drvdata(csdev->dev.parent)
 
+/* power management handling */
+static int nr_cti_cpu;
+
+/* quick lookup list for CPU bound CTIs when power handling */
+static struct cti_drvdata *cti_cpu_drvdata[NR_CPUS];
+
 /*
  * CTI naming. CTI bound to cores will have the name cti_cpu<N> where
  * N is the CPU ID. System CTIs will have the name cti_sys<I> where I
@@ -129,6 +136,35 @@ static int cti_enable_hw(struct cti_drvdata *drvdata)
 	return rc;
 }
 
+/* re-enable CTI on CPU when using CPU hotplug */
+static void cti_cpuhp_enable_hw(struct cti_drvdata *drvdata)
+{
+	struct cti_config *config = &drvdata->config;
+	struct device *dev = &drvdata->csdev->dev;
+
+	pm_runtime_get_sync(dev->parent);
+	spin_lock(&drvdata->spinlock);
+	config->hw_powered = true;
+
+	/* no need to do anything if no enable request */
+	if (!atomic_read(&drvdata->config.enable_req_count))
+		goto cti_hp_not_enabled;
+
+	/* try to claim the device */
+	if (coresight_claim_device(drvdata->base))
+		goto cti_hp_not_enabled;
+
+	cti_write_all_hw_regs(drvdata);
+	config->hw_enabled = true;
+	spin_unlock(&drvdata->spinlock);
+	return;
+
+	/* did not re-enable due to no claim / no request */
+cti_hp_not_enabled:
+	spin_unlock(&drvdata->spinlock);
+	pm_runtime_put(dev->parent);
+}
+
 /* disable hardware */
 static int cti_disable_hw(struct cti_drvdata *drvdata)
 {
@@ -620,6 +656,44 @@ static void cti_remove_conn_xrefs(struct cti_drvdata *drvdata)
 	}
 }
 
+/* CPU HP handlers */
+static int cti_starting_cpu(unsigned int cpu)
+{
+	struct cti_drvdata *drvdata = cti_cpu_drvdata[cpu];
+
+	if (!drvdata)
+		return 0;
+
+	cti_cpuhp_enable_hw(drvdata);
+	return 0;
+}
+
+static int cti_dying_cpu(unsigned int cpu)
+{
+	struct cti_drvdata *drvdata = cti_cpu_drvdata[cpu];
+
+	if (!drvdata)
+		return 0;
+
+	spin_lock(&drvdata->spinlock);
+	drvdata->config.hw_powered = false;
+	coresight_disclaim_device(drvdata->base);
+	spin_unlock(&drvdata->spinlock);
+	return 0;
+}
+
+/* release PM registrations */
+static void cti_pm_release(struct cti_drvdata *drvdata)
+{
+	if (drvdata->ctidev.cpu >= 0) {
+		if (--nr_cti_cpu == 0) {
+			cpuhp_remove_state_nocalls(
+				CPUHP_AP_ARM_CORESIGHT_CTI_STARTING);
+		}
+		cti_cpu_drvdata[drvdata->ctidev.cpu] = NULL;
+	}
+}
+
 /** cti ect operations **/
 int cti_enable(struct coresight_device *csdev)
 {
@@ -655,6 +729,7 @@ static void cti_device_release(struct device *dev)
 
 	mutex_lock(&ect_mutex);
 	cti_remove_conn_xrefs(drvdata);
+	cti_pm_release(drvdata);
 
 	/* remove from the list */
 	list_for_each_entry_safe(ect_item, ect_tmp, &ect_net, node) {
@@ -730,6 +805,22 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id)
 		goto err_out;
 	}
 
+	/* setup CPU power management handling for CPU bound CTI devices. */
+	if (drvdata->ctidev.cpu >= 0) {
+		cti_cpu_drvdata[drvdata->ctidev.cpu] = drvdata;
+		if (!nr_cti_cpu++) {
+			cpus_read_lock();
+			ret = cpuhp_setup_state_nocalls_cpuslocked(
+				CPUHP_AP_ARM_CORESIGHT_CTI_STARTING,
+				"arm/coresight_cti:starting",
+				cti_starting_cpu, cti_dying_cpu);
+
+			cpus_read_unlock();
+			if (ret)
+				goto err_out;
+		}
+	}
+
 	/* create dynamic attributes for connections */
 	ret = cti_create_cons_sysfs(dev, drvdata);
 	if (ret) {
@@ -768,6 +859,7 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id)
 	return 0;
 
 err_out:
+	cti_pm_release(drvdata);
 	return ret;
 }
 
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index 77d70b633531..6dc7332307ca 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -142,6 +142,7 @@ enum cpuhp_state {
 	CPUHP_AP_ARM_XEN_STARTING,
 	CPUHP_AP_ARM_KVMPV_STARTING,
 	CPUHP_AP_ARM_CORESIGHT_STARTING,
+	CPUHP_AP_ARM_CORESIGHT_CTI_STARTING,
 	CPUHP_AP_ARM64_ISNDEP_STARTING,
 	CPUHP_AP_SMPCFD_DYING,
 	CPUHP_AP_X86_TBOOT_DYING,
-- 
2.20.1


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  parent reply	other threads:[~2020-05-18 18:09 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-18 18:02 [PATCH 00/23] coresight: next for v5.8 Mathieu Poirier
2020-05-18 18:02 ` [PATCH 01/23] coresight: Pass coresight_device for coresight_release_platform_data Mathieu Poirier
2020-05-18 18:02 ` [PATCH 02/23] coresight: Add return value for fixup connections Mathieu Poirier
2020-05-18 18:02 ` [PATCH 03/23] coresight: Add generic sysfs link creation functions Mathieu Poirier
2020-05-18 18:02 ` [PATCH 04/23] coresight: Expose device connections via sysfs Mathieu Poirier
2020-05-18 18:02 ` [PATCH 05/23] coresight: cti: Add in sysfs links to other coresight devices Mathieu Poirier
2020-05-18 18:02 ` [PATCH 06/23] coresight: docs: Add information about the topology representations Mathieu Poirier
2020-05-18 18:02 ` [PATCH 07/23] docs: trace: coresight-ect.rst: Fix a build warning Mathieu Poirier
2020-05-18 18:02 ` [PATCH 08/23] coresight: etm4x: Add support for Qualcomm SC7180 SoC Mathieu Poirier
2020-05-18 18:02 ` [PATCH 09/23] coresight: etm4x: Replace ETM PIDs with UCI IDs for Kryo385 Mathieu Poirier
2020-05-18 18:02 ` [PATCH 10/23] coresight: cti: Make some symbols static Mathieu Poirier
2020-05-18 18:02 ` [PATCH 11/23] coresight: etb10: Make coresight_etb_groups static Mathieu Poirier
2020-05-18 18:02 ` [PATCH 12/23] coresight: Fix support for sparsely populated ports Mathieu Poirier
2020-05-18 18:02 ` [PATCH 13/23] coresight: tmc: Fix TMC mode read in tmc_read_prepare_etb() Mathieu Poirier
2020-05-18 18:02 ` [PATCH 14/23] coresight: etmv4: Update default filter and initialisation Mathieu Poirier
2020-05-18 18:02 ` [PATCH 15/23] coresight: etm4x: Add support for Neoverse N1 ETM Mathieu Poirier
2020-05-18 18:02 ` [PATCH 16/23] coresight: Mark some functions static Mathieu Poirier
2020-05-18 18:02 ` [PATCH 17/23] coresight: Don't initialize variables unnecessarily Mathieu Poirier
2020-05-18 18:02 ` [PATCH 18/23] coresight: Initialize arg in sparse friendly way Mathieu Poirier
2020-05-18 18:02 ` [PATCH 19/23] coresight: Include required headers in C files Mathieu Poirier
2020-05-18 18:02 ` [PATCH 20/23] coresight: Avoid casting void pointers Mathieu Poirier
2020-05-18 18:02 ` [PATCH 21/23] coresight: etm4x: Fix use-after-free of per-cpu etm drvdata Mathieu Poirier
2020-05-19 14:32   ` Greg KH
2020-05-18 18:02 ` Mathieu Poirier [this message]
2020-05-18 18:02 ` [PATCH 23/23] coresight: cti: Add CPU idle pm notifer to CTI devices Mathieu Poirier

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