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From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Subject: [Intel-gfx] [PATCH 01/10] drm/i915/gt: Set timeslicing priority from queue
Date: Fri,  5 Jun 2020 13:23:25 +0100	[thread overview]
Message-ID: <20200605122334.2798-1-chris@chris-wilson.co.uk> (raw)

If we only submit the first port, leaving the second empty yet have
ready requests pending in the queue, use that to set the timeslicing
priority (i.e. the priority at which we will decided to enabling
timeslicing and evict the currently active context if the queue is of
equal priority after its quantum expired).

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 33b7173b7195..92c3368ffcbd 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1966,7 +1966,7 @@ static int
 switch_prio(struct intel_engine_cs *engine, const struct i915_request *rq)
 {
 	if (list_is_last(&rq->sched.link, &engine->active.requests))
-		return INT_MIN;
+		return engine->execlists.queue_priority_hint;
 
 	return rq_prio(list_next_entry(rq, sched.link));
 }
-- 
2.20.1

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             reply	other threads:[~2020-06-05 12:23 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-05 12:23 Chris Wilson [this message]
2020-06-05 12:23 ` [Intel-gfx] [PATCH 02/10] drm/i915/gt: Always check to enable timeslicing if not submitting Chris Wilson
2020-06-05 15:20   ` Mika Kuoppala
2020-06-05 15:32     ` Chris Wilson
2020-06-05 15:34       ` Mika Kuoppala
2020-06-05 12:23 ` [Intel-gfx] [PATCH 03/10] Restore "drm/i915: drop engine_pin/unpin_breadcrumbs_irq" Chris Wilson
2020-06-05 15:30   ` Mika Kuoppala
2020-06-05 12:23 ` [Intel-gfx] [PATCH 04/10] drm/i915/gt: Couple tasklet scheduling for all CS interrupts Chris Wilson
2020-06-05 15:33   ` Mika Kuoppala
2020-06-05 15:40     ` Chris Wilson
2020-06-05 15:43       ` Mika Kuoppala
2020-06-05 12:23 ` [Intel-gfx] [PATCH 05/10] drm/i915/gt: Support creation of 'internal' rings Chris Wilson
2020-06-05 12:23 ` [Intel-gfx] [PATCH 06/10] drm/i915/gt: Use client timeline address for seqno writes Chris Wilson
2020-06-05 12:23 ` [Intel-gfx] [PATCH 07/10] drm/i915/gt: Infrastructure for ring scheduling Chris Wilson
2020-06-05 12:23 ` [Intel-gfx] [PATCH 08/10] drm/i915/gt: Enable busy-stats for ring-scheduler Chris Wilson
2020-06-05 12:23 ` [Intel-gfx] [PATCH 09/10] drm/i915/gt: Implement ring scheduler for gen6/7 Chris Wilson
2020-06-05 12:23 ` [Intel-gfx] [PATCH 10/10] drm/i915/gt: Enable ring scheduling " Chris Wilson
2020-06-05 12:38 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/10] drm/i915/gt: Set timeslicing priority from queue Patchwork
2020-06-05 12:39 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-06-05 13:00 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-06-05 14:28 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-06-05 14:47 ` [Intel-gfx] [PATCH 01/10] " Mika Kuoppala

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