From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org, qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Alistair Francis <alistair.francis@wdc.com>,
Richard Henderson <richard.henderson@linaro.org>,
LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PULL v2 17/64] target/riscv: vector single-width bit shift instructions
Date: Thu, 2 Jul 2020 09:23:07 -0700 [thread overview]
Message-ID: <20200702162354.928528-18-alistair.francis@wdc.com> (raw)
In-Reply-To: <20200702162354.928528-1-alistair.francis@wdc.com>
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-15-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/helper.h | 25 ++++++++
target/riscv/insn32.decode | 9 +++
target/riscv/insn_trans/trans_rvv.inc.c | 52 ++++++++++++++++
target/riscv/vector_helper.c | 79 +++++++++++++++++++++++++
4 files changed, 165 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index f8b1c8a800..6805bf7dbd 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -407,3 +407,28 @@ DEF_HELPER_6(vxor_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vxor_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vxor_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vxor_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(vsll_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsll_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsll_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsll_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsrl_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsrl_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsrl_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsrl_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsra_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsra_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsra_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsra_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsll_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsll_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsll_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsll_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsrl_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsrl_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsrl_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsrl_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsra_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsra_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsra_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsra_vx_d, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 34d05a5917..e5334230df 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -322,6 +322,15 @@ vor_vi 001010 . ..... ..... 011 ..... 1010111 @r_vm
vxor_vv 001011 . ..... ..... 000 ..... 1010111 @r_vm
vxor_vx 001011 . ..... ..... 100 ..... 1010111 @r_vm
vxor_vi 001011 . ..... ..... 011 ..... 1010111 @r_vm
+vsll_vv 100101 . ..... ..... 000 ..... 1010111 @r_vm
+vsll_vx 100101 . ..... ..... 100 ..... 1010111 @r_vm
+vsll_vi 100101 . ..... ..... 011 ..... 1010111 @r_vm
+vsrl_vv 101000 . ..... ..... 000 ..... 1010111 @r_vm
+vsrl_vx 101000 . ..... ..... 100 ..... 1010111 @r_vm
+vsrl_vi 101000 . ..... ..... 011 ..... 1010111 @r_vm
+vsra_vv 101001 . ..... ..... 000 ..... 1010111 @r_vm
+vsra_vx 101001 . ..... ..... 100 ..... 1010111 @r_vm
+vsra_vi 101001 . ..... ..... 011 ..... 1010111 @r_vm
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 1552534796..d2dbf701c8 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1373,3 +1373,55 @@ GEN_OPIVX_GVEC_TRANS(vxor_vx, xors)
GEN_OPIVI_GVEC_TRANS(vand_vi, 0, vand_vx, andi)
GEN_OPIVI_GVEC_TRANS(vor_vi, 0, vor_vx, ori)
GEN_OPIVI_GVEC_TRANS(vxor_vi, 0, vxor_vx, xori)
+
+/* Vector Single-Width Bit Shift Instructions */
+GEN_OPIVV_GVEC_TRANS(vsll_vv, shlv)
+GEN_OPIVV_GVEC_TRANS(vsrl_vv, shrv)
+GEN_OPIVV_GVEC_TRANS(vsra_vv, sarv)
+
+typedef void GVecGen2sFn32(unsigned, uint32_t, uint32_t, TCGv_i32,
+ uint32_t, uint32_t);
+
+static inline bool
+do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn,
+ gen_helper_opivx *fn)
+{
+ if (!opivx_check(s, a)) {
+ return false;
+ }
+
+ if (a->vm && s->vl_eq_vlmax) {
+ TCGv_i32 src1 = tcg_temp_new_i32();
+ TCGv tmp = tcg_temp_new();
+
+ gen_get_gpr(tmp, a->rs1);
+ tcg_gen_trunc_tl_i32(src1, tmp);
+ tcg_gen_extract_i32(src1, src1, 0, s->sew + 3);
+ gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
+ src1, MAXSZ(s), MAXSZ(s));
+
+ tcg_temp_free_i32(src1);
+ tcg_temp_free(tmp);
+ return true;
+ }
+ return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
+}
+
+#define GEN_OPIVX_GVEC_SHIFT_TRANS(NAME, SUF) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ static gen_helper_opivx * const fns[4] = { \
+ gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
+ gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
+ }; \
+ \
+ return do_opivx_gvec_shift(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \
+}
+
+GEN_OPIVX_GVEC_SHIFT_TRANS(vsll_vx, shls)
+GEN_OPIVX_GVEC_SHIFT_TRANS(vsrl_vx, shrs)
+GEN_OPIVX_GVEC_SHIFT_TRANS(vsra_vx, sars)
+
+GEN_OPIVI_GVEC_TRANS(vsll_vi, 1, vsll_vx, shli)
+GEN_OPIVI_GVEC_TRANS(vsrl_vi, 1, vsrl_vx, shri)
+GEN_OPIVI_GVEC_TRANS(vsra_vi, 1, vsra_vx, sari)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index bd77de110e..cd81f86faf 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -1316,3 +1316,82 @@ GEN_VEXT_VX(vxor_vx_b, 1, 1, clearb)
GEN_VEXT_VX(vxor_vx_h, 2, 2, clearh)
GEN_VEXT_VX(vxor_vx_w, 4, 4, clearl)
GEN_VEXT_VX(vxor_vx_d, 8, 8, clearq)
+
+/* Vector Single-Width Bit Shift Instructions */
+#define DO_SLL(N, M) (N << (M))
+#define DO_SRL(N, M) (N >> (M))
+
+/* generate the helpers for shift instructions with two vector operators */
+#define GEN_VEXT_SHIFT_VV(NAME, TS1, TS2, HS1, HS2, OP, MASK, CLEAR_FN) \
+void HELPER(NAME)(void *vd, void *v0, void *vs1, \
+ void *vs2, CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t mlen = vext_mlen(desc); \
+ uint32_t vm = vext_vm(desc); \
+ uint32_t vl = env->vl; \
+ uint32_t esz = sizeof(TS1); \
+ uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t i; \
+ \
+ for (i = 0; i < vl; i++) { \
+ if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ continue; \
+ } \
+ TS1 s1 = *((TS1 *)vs1 + HS1(i)); \
+ TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
+ *((TS1 *)vd + HS1(i)) = OP(s2, s1 & MASK); \
+ } \
+ CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
+}
+
+GEN_VEXT_SHIFT_VV(vsll_vv_b, uint8_t, uint8_t, H1, H1, DO_SLL, 0x7, clearb)
+GEN_VEXT_SHIFT_VV(vsll_vv_h, uint16_t, uint16_t, H2, H2, DO_SLL, 0xf, clearh)
+GEN_VEXT_SHIFT_VV(vsll_vv_w, uint32_t, uint32_t, H4, H4, DO_SLL, 0x1f, clearl)
+GEN_VEXT_SHIFT_VV(vsll_vv_d, uint64_t, uint64_t, H8, H8, DO_SLL, 0x3f, clearq)
+
+GEN_VEXT_SHIFT_VV(vsrl_vv_b, uint8_t, uint8_t, H1, H1, DO_SRL, 0x7, clearb)
+GEN_VEXT_SHIFT_VV(vsrl_vv_h, uint16_t, uint16_t, H2, H2, DO_SRL, 0xf, clearh)
+GEN_VEXT_SHIFT_VV(vsrl_vv_w, uint32_t, uint32_t, H4, H4, DO_SRL, 0x1f, clearl)
+GEN_VEXT_SHIFT_VV(vsrl_vv_d, uint64_t, uint64_t, H8, H8, DO_SRL, 0x3f, clearq)
+
+GEN_VEXT_SHIFT_VV(vsra_vv_b, uint8_t, int8_t, H1, H1, DO_SRL, 0x7, clearb)
+GEN_VEXT_SHIFT_VV(vsra_vv_h, uint16_t, int16_t, H2, H2, DO_SRL, 0xf, clearh)
+GEN_VEXT_SHIFT_VV(vsra_vv_w, uint32_t, int32_t, H4, H4, DO_SRL, 0x1f, clearl)
+GEN_VEXT_SHIFT_VV(vsra_vv_d, uint64_t, int64_t, H8, H8, DO_SRL, 0x3f, clearq)
+
+/* generate the helpers for shift instructions with one vector and one scalar */
+#define GEN_VEXT_SHIFT_VX(NAME, TD, TS2, HD, HS2, OP, MASK, CLEAR_FN) \
+void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
+ void *vs2, CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t mlen = vext_mlen(desc); \
+ uint32_t vm = vext_vm(desc); \
+ uint32_t vl = env->vl; \
+ uint32_t esz = sizeof(TD); \
+ uint32_t vlmax = vext_maxsz(desc) / esz; \
+ uint32_t i; \
+ \
+ for (i = 0; i < vl; i++) { \
+ if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ continue; \
+ } \
+ TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
+ *((TD *)vd + HD(i)) = OP(s2, s1 & MASK); \
+ } \
+ CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
+}
+
+GEN_VEXT_SHIFT_VX(vsll_vx_b, uint8_t, int8_t, H1, H1, DO_SLL, 0x7, clearb)
+GEN_VEXT_SHIFT_VX(vsll_vx_h, uint16_t, int16_t, H2, H2, DO_SLL, 0xf, clearh)
+GEN_VEXT_SHIFT_VX(vsll_vx_w, uint32_t, int32_t, H4, H4, DO_SLL, 0x1f, clearl)
+GEN_VEXT_SHIFT_VX(vsll_vx_d, uint64_t, int64_t, H8, H8, DO_SLL, 0x3f, clearq)
+
+GEN_VEXT_SHIFT_VX(vsrl_vx_b, uint8_t, uint8_t, H1, H1, DO_SRL, 0x7, clearb)
+GEN_VEXT_SHIFT_VX(vsrl_vx_h, uint16_t, uint16_t, H2, H2, DO_SRL, 0xf, clearh)
+GEN_VEXT_SHIFT_VX(vsrl_vx_w, uint32_t, uint32_t, H4, H4, DO_SRL, 0x1f, clearl)
+GEN_VEXT_SHIFT_VX(vsrl_vx_d, uint64_t, uint64_t, H8, H8, DO_SRL, 0x3f, clearq)
+
+GEN_VEXT_SHIFT_VX(vsra_vx_b, int8_t, int8_t, H1, H1, DO_SRL, 0x7, clearb)
+GEN_VEXT_SHIFT_VX(vsra_vx_h, int16_t, int16_t, H2, H2, DO_SRL, 0xf, clearh)
+GEN_VEXT_SHIFT_VX(vsra_vx_w, int32_t, int32_t, H4, H4, DO_SRL, 0x1f, clearl)
+GEN_VEXT_SHIFT_VX(vsra_vx_d, int64_t, int64_t, H8, H8, DO_SRL, 0x3f, clearq)
--
2.27.0
next prev parent reply other threads:[~2020-07-02 16:43 UTC|newest]
Thread overview: 73+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-02 16:22 [PULL v2 00/64] riscv-to-apply queue Alistair Francis
2020-07-02 16:22 ` [PULL v2 01/64] riscv: plic: Honour source priorities Alistair Francis
2020-07-02 16:22 ` [PULL v2 02/64] riscv: plic: Add a couple of mising sifive_plic_update calls Alistair Francis
2020-07-02 16:22 ` [PULL v2 03/64] hw/riscv: Allow 64 bit access to SiFive CLINT Alistair Francis
2020-07-02 16:22 ` [PULL v2 04/64] target/riscv: add vector extension field in CPURISCVState Alistair Francis
2020-07-02 16:22 ` [PULL v2 05/64] target/riscv: implementation-defined constant parameters Alistair Francis
2020-07-02 16:22 ` [PULL v2 06/64] target/riscv: support vector extension csr Alistair Francis
2020-07-02 16:22 ` [PULL v2 07/64] target/riscv: add vector configure instruction Alistair Francis
2020-07-02 16:22 ` [PULL v2 08/64] target/riscv: add an internals.h header Alistair Francis
2020-07-02 16:22 ` [PULL v2 09/64] target/riscv: add vector stride load and store instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 10/64] target/riscv: add vector index " Alistair Francis
2020-07-02 16:23 ` [PULL v2 11/64] target/riscv: add fault-only-first unit stride load Alistair Francis
2020-07-02 16:23 ` [PULL v2 12/64] target/riscv: add vector amo operations Alistair Francis
2020-07-05 18:20 ` Peter Maydell
2020-07-06 20:48 ` Richard Henderson
2020-07-07 14:26 ` LIU Zhiwei
2020-07-07 14:33 ` Richard Henderson
2020-07-06 23:36 ` Alistair Francis
2020-07-07 2:35 ` LIU Zhiwei
2020-07-02 16:23 ` [PULL v2 13/64] target/riscv: vector single-width integer add and subtract Alistair Francis
2020-07-02 16:23 ` [PULL v2 14/64] target/riscv: vector widening " Alistair Francis
2020-07-02 16:23 ` [PULL v2 15/64] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 16/64] target/riscv: vector bitwise logical instructions Alistair Francis
2020-07-02 16:23 ` Alistair Francis [this message]
2020-07-02 16:23 ` [PULL v2 18/64] target/riscv: vector narrowing integer right shift instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 19/64] target/riscv: vector integer comparison instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 20/64] target/riscv: vector integer min/max instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 21/64] target/riscv: vector single-width integer multiply instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 22/64] target/riscv: vector integer divide instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 23/64] target/riscv: vector widening integer multiply instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 24/64] target/riscv: vector single-width integer multiply-add instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 25/64] target/riscv: vector widening " Alistair Francis
2020-07-02 16:23 ` [PULL v2 26/64] target/riscv: vector integer merge and move instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 27/64] target/riscv: vector single-width saturating add and subtract Alistair Francis
2020-07-02 16:23 ` [PULL v2 28/64] target/riscv: vector single-width averaging " Alistair Francis
2020-07-02 16:23 ` [PULL v2 29/64] target/riscv: vector single-width fractional multiply with rounding and saturation Alistair Francis
2020-07-02 16:23 ` [PULL v2 30/64] target/riscv: vector widening saturating scaled multiply-add Alistair Francis
2020-07-02 16:23 ` [PULL v2 31/64] target/riscv: vector single-width scaling shift instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 32/64] target/riscv: vector narrowing fixed-point clip instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 33/64] target/riscv: vector single-width floating-point add/subtract instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 34/64] target/riscv: vector widening " Alistair Francis
2020-07-02 16:23 ` [PULL v2 35/64] target/riscv: vector single-width floating-point multiply/divide instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 36/64] target/riscv: vector widening floating-point multiply Alistair Francis
2020-07-02 16:23 ` [PULL v2 37/64] target/riscv: vector single-width floating-point fused multiply-add instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 38/64] target/riscv: vector widening " Alistair Francis
2020-07-02 16:23 ` [PULL v2 39/64] target/riscv: vector floating-point square-root instruction Alistair Francis
2020-07-02 16:23 ` [PULL v2 40/64] target/riscv: vector floating-point min/max instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 41/64] target/riscv: vector floating-point sign-injection instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 42/64] target/riscv: vector floating-point compare instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 43/64] target/riscv: vector floating-point classify instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 44/64] target/riscv: vector floating-point merge instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 45/64] target/riscv: vector floating-point/integer type-convert instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 46/64] target/riscv: widening " Alistair Francis
2020-07-02 16:23 ` [PULL v2 47/64] target/riscv: narrowing " Alistair Francis
2020-07-02 16:23 ` [PULL v2 48/64] target/riscv: vector single-width integer reduction instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 49/64] target/riscv: vector wideing " Alistair Francis
2020-07-02 16:23 ` [PULL v2 50/64] target/riscv: vector single-width floating-point " Alistair Francis
2020-07-02 16:23 ` [PULL v2 51/64] target/riscv: vector widening " Alistair Francis
2020-07-02 16:23 ` [PULL v2 52/64] target/riscv: vector mask-register logical instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 53/64] target/riscv: vector mask population count vmpopc Alistair Francis
2020-07-02 16:23 ` [PULL v2 54/64] target/riscv: vmfirst find-first-set mask bit Alistair Francis
2020-07-02 16:23 ` [PULL v2 55/64] target/riscv: set-X-first " Alistair Francis
2020-07-02 16:23 ` [PULL v2 56/64] target/riscv: vector iota instruction Alistair Francis
2020-07-02 16:23 ` [PULL v2 57/64] target/riscv: vector element index instruction Alistair Francis
2020-07-02 16:23 ` [PULL v2 58/64] target/riscv: integer extract instruction Alistair Francis
2020-07-02 16:23 ` [PULL v2 59/64] target/riscv: integer scalar move instruction Alistair Francis
2020-07-02 16:23 ` [PULL v2 60/64] target/riscv: floating-point scalar move instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 61/64] target/riscv: vector slide instructions Alistair Francis
2020-07-02 16:23 ` [PULL v2 62/64] target/riscv: vector register gather instruction Alistair Francis
2020-07-02 16:23 ` [PULL v2 63/64] target/riscv: vector compress instruction Alistair Francis
2020-07-02 16:23 ` [PULL v2 64/64] target/riscv: configure and turn on vector extension from command line Alistair Francis
2020-07-02 17:27 ` [PULL v2 00/64] riscv-to-apply queue no-reply
2020-07-03 16:55 ` Peter Maydell
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