From: Jordan Crouse <jcrouse@codeaurora.org>
To: Rob Clark <robdclark@gmail.com>
Cc: dri-devel@lists.freedesktop.org,
Rob Clark <robdclark@chromium.org>, Sean Paul <sean@poorly.run>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Jonathan Marek <jonathan@marek.ca>,
Sharat Masetty <smasetty@codeaurora.org>,
Jeffrey Hugo <jeffrey.l.hugo@gmail.com>,
Harigovindan P <harigovi@codeaurora.org>,
Linus Walleij <linus.walleij@linaro.org>,
Sam Ravnborg <sam@ravnborg.org>, zhengbin <zhengbin13@huawei.com>,
"open list:DRM DRIVER FOR MSM ADRENO GPU"
<linux-arm-msm@vger.kernel.org>,
"open list:DRM DRIVER FOR MSM ADRENO GPU"
<freedreno@lists.freedesktop.org>,
open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/2] drm/msm: sync generated headers
Date: Fri, 10 Jul 2020 12:02:01 -0600 [thread overview]
Message-ID: <20200710180201.GF21059@jcrouse1-lnx.qualcomm.com> (raw)
In-Reply-To: <20200707203529.2098979-2-robdclark@gmail.com>
On Tue, Jul 07, 2020 at 01:34:59PM -0700, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
>
> We haven't sync'd for a while.. pull in updates to get definitions for
> some fields in pkt7 payloads.
Acked-by: Jordan Crouse <jcrouse@codeaurora.org>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
> drivers/gpu/drm/msm/adreno/a2xx.xml.h | 1102 +++++++-
> drivers/gpu/drm/msm/adreno/a3xx.xml.h | 85 +-
> drivers/gpu/drm/msm/adreno/a4xx.xml.h | 87 +-
> drivers/gpu/drm/msm/adreno/a5xx.xml.h | 156 +-
> drivers/gpu/drm/msm/adreno/a6xx.xml.h | 2305 ++++++++++++++---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 28 +-
> .../gpu/drm/msm/adreno/adreno_common.xml.h | 29 +-
> drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h | 932 ++++++-
> drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h | 2 +-
> drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h | 2 +-
> drivers/gpu/drm/msm/disp/mdp_common.xml.h | 2 +-
> drivers/gpu/drm/msm/dsi/dsi.xml.h | 208 +-
> drivers/gpu/drm/msm/dsi/dsi_host.c | 14 +-
> drivers/gpu/drm/msm/dsi/mmss_cc.xml.h | 2 +-
> drivers/gpu/drm/msm/dsi/sfpb.xml.h | 2 +-
> drivers/gpu/drm/msm/edp/edp.xml.h | 2 +-
> drivers/gpu/drm/msm/hdmi/hdmi.xml.h | 2 +-
> drivers/gpu/drm/msm/hdmi/qfprom.xml.h | 2 +-
> 18 files changed, 4318 insertions(+), 644 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a2xx.xml.h b/drivers/gpu/drm/msm/adreno/a2xx.xml.h
> index 14eb52f3e605..7e49e50c6d9e 100644
> --- a/drivers/gpu/drm/msm/adreno/a2xx.xml.h
> +++ b/drivers/gpu/drm/msm/adreno/a2xx.xml.h
> @@ -8,19 +8,21 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
> git clone https://github.com/freedreno/envytools.git
>
> The rules-ng-ng source files this header was generated from are:
> -- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 42463 bytes, from 2018-11-19 13:44:03)
> -- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14201 bytes, from 2018-12-02 17:29:54)
> -- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43052 bytes, from 2018-12-02 17:29:54)
> -- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-02 17:29:54)
> -- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 140790 bytes, from 2018-12-02 17:29:54)
> -- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
> -- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
> -
> -Copyright (C) 2013-2018 by the following authors:
> +- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-06-21 22:29:16)
> +- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
> +- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 89649 bytes, from 2020-07-04 19:55:04)
> +- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14239 bytes, from 2020-07-04 19:55:04)
> +- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 63258 bytes, from 2020-07-07 19:26:50)
> +- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84246 bytes, from 2020-07-04 19:55:04)
> +- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112247 bytes, from 2020-07-04 19:55:04)
> +- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 148499 bytes, from 2020-07-04 20:00:49)
> +- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 174474 bytes, from 2020-07-04 20:56:59)
> +- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10768 bytes, from 2020-05-20 19:42:03)
> +- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
> +- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-06-21 22:29:16)
> +- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-06-21 22:29:43)
> +
> +Copyright (C) 2013-2020 by the following authors:
> - Rob Clark <robdclark@gmail.com> (robclark)
> - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
>
> @@ -210,6 +212,854 @@ enum a2xx_rb_blend_opcode {
> BLEND2_DST_PLUS_SRC_BIAS = 5,
> };
>
> +enum a2xx_su_perfcnt_select {
> + PERF_PAPC_PASX_REQ = 0,
> + PERF_PAPC_PASX_FIRST_VECTOR = 2,
> + PERF_PAPC_PASX_SECOND_VECTOR = 3,
> + PERF_PAPC_PASX_FIRST_DEAD = 4,
> + PERF_PAPC_PASX_SECOND_DEAD = 5,
> + PERF_PAPC_PASX_VTX_KILL_DISCARD = 6,
> + PERF_PAPC_PASX_VTX_NAN_DISCARD = 7,
> + PERF_PAPC_PA_INPUT_PRIM = 8,
> + PERF_PAPC_PA_INPUT_NULL_PRIM = 9,
> + PERF_PAPC_PA_INPUT_EVENT_FLAG = 10,
> + PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11,
> + PERF_PAPC_PA_INPUT_END_OF_PACKET = 12,
> + PERF_PAPC_CLPR_CULL_PRIM = 13,
> + PERF_PAPC_CLPR_VV_CULL_PRIM = 15,
> + PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 17,
> + PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 18,
> + PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 19,
> + PERF_PAPC_CLPR_VV_CLIP_PRIM = 21,
> + PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 23,
> + PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 24,
> + PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 25,
> + PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 26,
> + PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 27,
> + PERF_PAPC_CLPR_CLIP_PLANE_CNT_5 = 28,
> + PERF_PAPC_CLPR_CLIP_PLANE_CNT_6 = 29,
> + PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 30,
> + PERF_PAPC_CLPR_CLIP_PLANE_FAR = 31,
> + PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 32,
> + PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 33,
> + PERF_PAPC_CLPR_CLIP_PLANE_TOP = 34,
> + PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 35,
> + PERF_PAPC_CLSM_NULL_PRIM = 36,
> + PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 37,
> + PERF_PAPC_CLSM_CLIP_PRIM = 38,
> + PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 39,
> + PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 40,
> + PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 41,
> + PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 42,
> + PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 43,
> + PERF_PAPC_CLSM_OUT_PRIM_CNT_5 = 44,
> + PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7 = 45,
> + PERF_PAPC_CLSM_NON_TRIVIAL_CULL = 46,
> + PERF_PAPC_SU_INPUT_PRIM = 47,
> + PERF_PAPC_SU_INPUT_CLIP_PRIM = 48,
> + PERF_PAPC_SU_INPUT_NULL_PRIM = 49,
> + PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 50,
> + PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 51,
> + PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 52,
> + PERF_PAPC_SU_POLYMODE_FACE_CULL = 53,
> + PERF_PAPC_SU_POLYMODE_BACK_CULL = 54,
> + PERF_PAPC_SU_POLYMODE_FRONT_CULL = 55,
> + PERF_PAPC_SU_POLYMODE_INVALID_FILL = 56,
> + PERF_PAPC_SU_OUTPUT_PRIM = 57,
> + PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 58,
> + PERF_PAPC_SU_OUTPUT_NULL_PRIM = 59,
> + PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 60,
> + PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 61,
> + PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 62,
> + PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 63,
> + PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 64,
> + PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 65,
> + PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 66,
> + PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 67,
> + PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 68,
> + PERF_PAPC_PASX_REQ_IDLE = 69,
> + PERF_PAPC_PASX_REQ_BUSY = 70,
> + PERF_PAPC_PASX_REQ_STALLED = 71,
> + PERF_PAPC_PASX_REC_IDLE = 72,
> + PERF_PAPC_PASX_REC_BUSY = 73,
> + PERF_PAPC_PASX_REC_STARVED_SX = 74,
> + PERF_PAPC_PASX_REC_STALLED = 75,
> + PERF_PAPC_PASX_REC_STALLED_POS_MEM = 76,
> + PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 77,
> + PERF_PAPC_CCGSM_IDLE = 78,
> + PERF_PAPC_CCGSM_BUSY = 79,
> + PERF_PAPC_CCGSM_STALLED = 80,
> + PERF_PAPC_CLPRIM_IDLE = 81,
> + PERF_PAPC_CLPRIM_BUSY = 82,
> + PERF_PAPC_CLPRIM_STALLED = 83,
> + PERF_PAPC_CLPRIM_STARVED_CCGSM = 84,
> + PERF_PAPC_CLIPSM_IDLE = 85,
> + PERF_PAPC_CLIPSM_BUSY = 86,
> + PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 87,
> + PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 88,
> + PERF_PAPC_CLIPSM_WAIT_CLIPGA = 89,
> + PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 90,
> + PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 91,
> + PERF_PAPC_CLIPGA_IDLE = 92,
> + PERF_PAPC_CLIPGA_BUSY = 93,
> + PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 94,
> + PERF_PAPC_CLIPGA_STALLED = 95,
> + PERF_PAPC_CLIP_IDLE = 96,
> + PERF_PAPC_CLIP_BUSY = 97,
> + PERF_PAPC_SU_IDLE = 98,
> + PERF_PAPC_SU_BUSY = 99,
> + PERF_PAPC_SU_STARVED_CLIP = 100,
> + PERF_PAPC_SU_STALLED_SC = 101,
> + PERF_PAPC_SU_FACENESS_CULL = 102,
> +};
> +
> +enum a2xx_sc_perfcnt_select {
> + SC_SR_WINDOW_VALID = 0,
> + SC_CW_WINDOW_VALID = 1,
> + SC_QM_WINDOW_VALID = 2,
> + SC_FW_WINDOW_VALID = 3,
> + SC_EZ_WINDOW_VALID = 4,
> + SC_IT_WINDOW_VALID = 5,
> + SC_STARVED_BY_PA = 6,
> + SC_STALLED_BY_RB_TILE = 7,
> + SC_STALLED_BY_RB_SAMP = 8,
> + SC_STARVED_BY_RB_EZ = 9,
> + SC_STALLED_BY_SAMPLE_FF = 10,
> + SC_STALLED_BY_SQ = 11,
> + SC_STALLED_BY_SP = 12,
> + SC_TOTAL_NO_PRIMS = 13,
> + SC_NON_EMPTY_PRIMS = 14,
> + SC_NO_TILES_PASSING_QM = 15,
> + SC_NO_PIXELS_PRE_EZ = 16,
> + SC_NO_PIXELS_POST_EZ = 17,
> +};
> +
> +enum a2xx_vgt_perfcount_select {
> + VGT_SQ_EVENT_WINDOW_ACTIVE = 0,
> + VGT_SQ_SEND = 1,
> + VGT_SQ_STALLED = 2,
> + VGT_SQ_STARVED_BUSY = 3,
> + VGT_SQ_STARVED_IDLE = 4,
> + VGT_SQ_STATIC = 5,
> + VGT_PA_EVENT_WINDOW_ACTIVE = 6,
> + VGT_PA_CLIP_V_SEND = 7,
> + VGT_PA_CLIP_V_STALLED = 8,
> + VGT_PA_CLIP_V_STARVED_BUSY = 9,
> + VGT_PA_CLIP_V_STARVED_IDLE = 10,
> + VGT_PA_CLIP_V_STATIC = 11,
> + VGT_PA_CLIP_P_SEND = 12,
> + VGT_PA_CLIP_P_STALLED = 13,
> + VGT_PA_CLIP_P_STARVED_BUSY = 14,
> + VGT_PA_CLIP_P_STARVED_IDLE = 15,
> + VGT_PA_CLIP_P_STATIC = 16,
> + VGT_PA_CLIP_S_SEND = 17,
> + VGT_PA_CLIP_S_STALLED = 18,
> + VGT_PA_CLIP_S_STARVED_BUSY = 19,
> + VGT_PA_CLIP_S_STARVED_IDLE = 20,
> + VGT_PA_CLIP_S_STATIC = 21,
> + RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 22,
> + RBIU_IMMED_DATA_FIFO_STARVED = 23,
> + RBIU_IMMED_DATA_FIFO_STALLED = 24,
> + RBIU_DMA_REQUEST_FIFO_STARVED = 25,
> + RBIU_DMA_REQUEST_FIFO_STALLED = 26,
> + RBIU_DRAW_INITIATOR_FIFO_STARVED = 27,
> + RBIU_DRAW_INITIATOR_FIFO_STALLED = 28,
> + BIN_PRIM_NEAR_CULL = 29,
> + BIN_PRIM_ZERO_CULL = 30,
> + BIN_PRIM_FAR_CULL = 31,
> + BIN_PRIM_BIN_CULL = 32,
> + BIN_PRIM_FACE_CULL = 33,
> + SPARE34 = 34,
> + SPARE35 = 35,
> + SPARE36 = 36,
> + SPARE37 = 37,
> + SPARE38 = 38,
> + SPARE39 = 39,
> + TE_SU_IN_VALID = 40,
> + TE_SU_IN_READ = 41,
> + TE_SU_IN_PRIM = 42,
> + TE_SU_IN_EOP = 43,
> + TE_SU_IN_NULL_PRIM = 44,
> + TE_WK_IN_VALID = 45,
> + TE_WK_IN_READ = 46,
> + TE_OUT_PRIM_VALID = 47,
> + TE_OUT_PRIM_READ = 48,
> +};
> +
> +enum a2xx_tcr_perfcount_select {
> + DGMMPD_IPMUX0_STALL = 0,
> + DGMMPD_IPMUX_ALL_STALL = 4,
> + OPMUX0_L2_WRITES = 5,
> +};
> +
> +enum a2xx_tp_perfcount_select {
> + POINT_QUADS = 0,
> + BILIN_QUADS = 1,
> + ANISO_QUADS = 2,
> + MIP_QUADS = 3,
> + VOL_QUADS = 4,
> + MIP_VOL_QUADS = 5,
> + MIP_ANISO_QUADS = 6,
> + VOL_ANISO_QUADS = 7,
> + ANISO_2_1_QUADS = 8,
> + ANISO_4_1_QUADS = 9,
> + ANISO_6_1_QUADS = 10,
> + ANISO_8_1_QUADS = 11,
> + ANISO_10_1_QUADS = 12,
> + ANISO_12_1_QUADS = 13,
> + ANISO_14_1_QUADS = 14,
> + ANISO_16_1_QUADS = 15,
> + MIP_VOL_ANISO_QUADS = 16,
> + ALIGN_2_QUADS = 17,
> + ALIGN_4_QUADS = 18,
> + PIX_0_QUAD = 19,
> + PIX_1_QUAD = 20,
> + PIX_2_QUAD = 21,
> + PIX_3_QUAD = 22,
> + PIX_4_QUAD = 23,
> + TP_MIPMAP_LOD0 = 24,
> + TP_MIPMAP_LOD1 = 25,
> + TP_MIPMAP_LOD2 = 26,
> + TP_MIPMAP_LOD3 = 27,
> + TP_MIPMAP_LOD4 = 28,
> + TP_MIPMAP_LOD5 = 29,
> + TP_MIPMAP_LOD6 = 30,
> + TP_MIPMAP_LOD7 = 31,
> + TP_MIPMAP_LOD8 = 32,
> + TP_MIPMAP_LOD9 = 33,
> + TP_MIPMAP_LOD10 = 34,
> + TP_MIPMAP_LOD11 = 35,
> + TP_MIPMAP_LOD12 = 36,
> + TP_MIPMAP_LOD13 = 37,
> + TP_MIPMAP_LOD14 = 38,
> +};
> +
> +enum a2xx_tcm_perfcount_select {
> + QUAD0_RD_LAT_FIFO_EMPTY = 0,
> + QUAD0_RD_LAT_FIFO_4TH_FULL = 3,
> + QUAD0_RD_LAT_FIFO_HALF_FULL = 4,
> + QUAD0_RD_LAT_FIFO_FULL = 5,
> + QUAD0_RD_LAT_FIFO_LT_4TH_FULL = 6,
> + READ_STARVED_QUAD0 = 28,
> + READ_STARVED = 32,
> + READ_STALLED_QUAD0 = 33,
> + READ_STALLED = 37,
> + VALID_READ_QUAD0 = 38,
> + TC_TP_STARVED_QUAD0 = 42,
> + TC_TP_STARVED = 46,
> +};
> +
> +enum a2xx_tcf_perfcount_select {
> + VALID_CYCLES = 0,
> + SINGLE_PHASES = 1,
> + ANISO_PHASES = 2,
> + MIP_PHASES = 3,
> + VOL_PHASES = 4,
> + MIP_VOL_PHASES = 5,
> + MIP_ANISO_PHASES = 6,
> + VOL_ANISO_PHASES = 7,
> + ANISO_2_1_PHASES = 8,
> + ANISO_4_1_PHASES = 9,
> + ANISO_6_1_PHASES = 10,
> + ANISO_8_1_PHASES = 11,
> + ANISO_10_1_PHASES = 12,
> + ANISO_12_1_PHASES = 13,
> + ANISO_14_1_PHASES = 14,
> + ANISO_16_1_PHASES = 15,
> + MIP_VOL_ANISO_PHASES = 16,
> + ALIGN_2_PHASES = 17,
> + ALIGN_4_PHASES = 18,
> + TPC_BUSY = 19,
> + TPC_STALLED = 20,
> + TPC_STARVED = 21,
> + TPC_WORKING = 22,
> + TPC_WALKER_BUSY = 23,
> + TPC_WALKER_STALLED = 24,
> + TPC_WALKER_WORKING = 25,
> + TPC_ALIGNER_BUSY = 26,
> + TPC_ALIGNER_STALLED = 27,
> + TPC_ALIGNER_STALLED_BY_BLEND = 28,
> + TPC_ALIGNER_STALLED_BY_CACHE = 29,
> + TPC_ALIGNER_WORKING = 30,
> + TPC_BLEND_BUSY = 31,
> + TPC_BLEND_SYNC = 32,
> + TPC_BLEND_STARVED = 33,
> + TPC_BLEND_WORKING = 34,
> + OPCODE_0x00 = 35,
> + OPCODE_0x01 = 36,
> + OPCODE_0x04 = 37,
> + OPCODE_0x10 = 38,
> + OPCODE_0x11 = 39,
> + OPCODE_0x12 = 40,
> + OPCODE_0x13 = 41,
> + OPCODE_0x18 = 42,
> + OPCODE_0x19 = 43,
> + OPCODE_0x1A = 44,
> + OPCODE_OTHER = 45,
> + IN_FIFO_0_EMPTY = 56,
> + IN_FIFO_0_LT_HALF_FULL = 57,
> + IN_FIFO_0_HALF_FULL = 58,
> + IN_FIFO_0_FULL = 59,
> + IN_FIFO_TPC_EMPTY = 72,
> + IN_FIFO_TPC_LT_HALF_FULL = 73,
> + IN_FIFO_TPC_HALF_FULL = 74,
> + IN_FIFO_TPC_FULL = 75,
> + TPC_TC_XFC = 76,
> + TPC_TC_STATE = 77,
> + TC_STALL = 78,
> + QUAD0_TAPS = 79,
> + QUADS = 83,
> + TCA_SYNC_STALL = 84,
> + TAG_STALL = 85,
> + TCB_SYNC_STALL = 88,
> + TCA_VALID = 89,
> + PROBES_VALID = 90,
> + MISS_STALL = 91,
> + FETCH_FIFO_STALL = 92,
> + TCO_STALL = 93,
> + ANY_STALL = 94,
> + TAG_MISSES = 95,
> + TAG_HITS = 96,
> + SUB_TAG_MISSES = 97,
> + SET0_INVALIDATES = 98,
> + SET1_INVALIDATES = 99,
> + SET2_INVALIDATES = 100,
> + SET3_INVALIDATES = 101,
> + SET0_TAG_MISSES = 102,
> + SET1_TAG_MISSES = 103,
> + SET2_TAG_MISSES = 104,
> + SET3_TAG_MISSES = 105,
> + SET0_TAG_HITS = 106,
> + SET1_TAG_HITS = 107,
> + SET2_TAG_HITS = 108,
> + SET3_TAG_HITS = 109,
> + SET0_SUB_TAG_MISSES = 110,
> + SET1_SUB_TAG_MISSES = 111,
> + SET2_SUB_TAG_MISSES = 112,
> + SET3_SUB_TAG_MISSES = 113,
> + SET0_EVICT1 = 114,
> + SET0_EVICT2 = 115,
> + SET0_EVICT3 = 116,
> + SET0_EVICT4 = 117,
> + SET0_EVICT5 = 118,
> + SET0_EVICT6 = 119,
> + SET0_EVICT7 = 120,
> + SET0_EVICT8 = 121,
> + SET1_EVICT1 = 130,
> + SET1_EVICT2 = 131,
> + SET1_EVICT3 = 132,
> + SET1_EVICT4 = 133,
> + SET1_EVICT5 = 134,
> + SET1_EVICT6 = 135,
> + SET1_EVICT7 = 136,
> + SET1_EVICT8 = 137,
> + SET2_EVICT1 = 146,
> + SET2_EVICT2 = 147,
> + SET2_EVICT3 = 148,
> + SET2_EVICT4 = 149,
> + SET2_EVICT5 = 150,
> + SET2_EVICT6 = 151,
> + SET2_EVICT7 = 152,
> + SET2_EVICT8 = 153,
> + SET3_EVICT1 = 162,
> + SET3_EVICT2 = 163,
> + SET3_EVICT3 = 164,
> + SET3_EVICT4 = 165,
> + SET3_EVICT5 = 166,
> + SET3_EVICT6 = 167,
> + SET3_EVICT7 = 168,
> + SET3_EVICT8 = 169,
> + FF_EMPTY = 178,
> + FF_LT_HALF_FULL = 179,
> + FF_HALF_FULL = 180,
> + FF_FULL = 181,
> + FF_XFC = 182,
> + FF_STALLED = 183,
> + FG_MASKS = 184,
> + FG_LEFT_MASKS = 185,
> + FG_LEFT_MASK_STALLED = 186,
> + FG_LEFT_NOT_DONE_STALL = 187,
> + FG_LEFT_FG_STALL = 188,
> + FG_LEFT_SECTORS = 189,
> + FG0_REQUESTS = 195,
> + FG0_STALLED = 196,
> + MEM_REQ512 = 199,
> + MEM_REQ_SENT = 200,
> + MEM_LOCAL_READ_REQ = 202,
> + TC0_MH_STALLED = 203,
> +};
> +
> +enum a2xx_sq_perfcnt_select {
> + SQ_PIXEL_VECTORS_SUB = 0,
> + SQ_VERTEX_VECTORS_SUB = 1,
> + SQ_ALU0_ACTIVE_VTX_SIMD0 = 2,
> + SQ_ALU1_ACTIVE_VTX_SIMD0 = 3,
> + SQ_ALU0_ACTIVE_PIX_SIMD0 = 4,
> + SQ_ALU1_ACTIVE_PIX_SIMD0 = 5,
> + SQ_ALU0_ACTIVE_VTX_SIMD1 = 6,
> + SQ_ALU1_ACTIVE_VTX_SIMD1 = 7,
> + SQ_ALU0_ACTIVE_PIX_SIMD1 = 8,
> + SQ_ALU1_ACTIVE_PIX_SIMD1 = 9,
> + SQ_EXPORT_CYCLES = 10,
> + SQ_ALU_CST_WRITTEN = 11,
> + SQ_TEX_CST_WRITTEN = 12,
> + SQ_ALU_CST_STALL = 13,
> + SQ_ALU_TEX_STALL = 14,
> + SQ_INST_WRITTEN = 15,
> + SQ_BOOLEAN_WRITTEN = 16,
> + SQ_LOOPS_WRITTEN = 17,
> + SQ_PIXEL_SWAP_IN = 18,
> + SQ_PIXEL_SWAP_OUT = 19,
> + SQ_VERTEX_SWAP_IN = 20,
> + SQ_VERTEX_SWAP_OUT = 21,
> + SQ_ALU_VTX_INST_ISSUED = 22,
> + SQ_TEX_VTX_INST_ISSUED = 23,
> + SQ_VC_VTX_INST_ISSUED = 24,
> + SQ_CF_VTX_INST_ISSUED = 25,
> + SQ_ALU_PIX_INST_ISSUED = 26,
> + SQ_TEX_PIX_INST_ISSUED = 27,
> + SQ_VC_PIX_INST_ISSUED = 28,
> + SQ_CF_PIX_INST_ISSUED = 29,
> + SQ_ALU0_FIFO_EMPTY_SIMD0 = 30,
> + SQ_ALU1_FIFO_EMPTY_SIMD0 = 31,
> + SQ_ALU0_FIFO_EMPTY_SIMD1 = 32,
> + SQ_ALU1_FIFO_EMPTY_SIMD1 = 33,
> + SQ_ALU_NOPS = 34,
> + SQ_PRED_SKIP = 35,
> + SQ_SYNC_ALU_STALL_SIMD0_VTX = 36,
> + SQ_SYNC_ALU_STALL_SIMD1_VTX = 37,
> + SQ_SYNC_TEX_STALL_VTX = 38,
> + SQ_SYNC_VC_STALL_VTX = 39,
> + SQ_CONSTANTS_USED_SIMD0 = 40,
> + SQ_CONSTANTS_SENT_SP_SIMD0 = 41,
> + SQ_GPR_STALL_VTX = 42,
> + SQ_GPR_STALL_PIX = 43,
> + SQ_VTX_RS_STALL = 44,
> + SQ_PIX_RS_STALL = 45,
> + SQ_SX_PC_FULL = 46,
> + SQ_SX_EXP_BUFF_FULL = 47,
> + SQ_SX_POS_BUFF_FULL = 48,
> + SQ_INTERP_QUADS = 49,
> + SQ_INTERP_ACTIVE = 50,
> + SQ_IN_PIXEL_STALL = 51,
> + SQ_IN_VTX_STALL = 52,
> + SQ_VTX_CNT = 53,
> + SQ_VTX_VECTOR2 = 54,
> + SQ_VTX_VECTOR3 = 55,
> + SQ_VTX_VECTOR4 = 56,
> + SQ_PIXEL_VECTOR1 = 57,
> + SQ_PIXEL_VECTOR23 = 58,
> + SQ_PIXEL_VECTOR4 = 59,
> + SQ_CONSTANTS_USED_SIMD1 = 60,
> + SQ_CONSTANTS_SENT_SP_SIMD1 = 61,
> + SQ_SX_MEM_EXP_FULL = 62,
> + SQ_ALU0_ACTIVE_VTX_SIMD2 = 63,
> + SQ_ALU1_ACTIVE_VTX_SIMD2 = 64,
> + SQ_ALU0_ACTIVE_PIX_SIMD2 = 65,
> + SQ_ALU1_ACTIVE_PIX_SIMD2 = 66,
> + SQ_ALU0_ACTIVE_VTX_SIMD3 = 67,
> + SQ_PERFCOUNT_VTX_QUAL_TP_DONE = 68,
> + SQ_ALU0_ACTIVE_PIX_SIMD3 = 69,
> + SQ_PERFCOUNT_PIX_QUAL_TP_DONE = 70,
> + SQ_ALU0_FIFO_EMPTY_SIMD2 = 71,
> + SQ_ALU1_FIFO_EMPTY_SIMD2 = 72,
> + SQ_ALU0_FIFO_EMPTY_SIMD3 = 73,
> + SQ_ALU1_FIFO_EMPTY_SIMD3 = 74,
> + SQ_SYNC_ALU_STALL_SIMD2_VTX = 75,
> + SQ_PERFCOUNT_VTX_POP_THREAD = 76,
> + SQ_SYNC_ALU_STALL_SIMD0_PIX = 77,
> + SQ_SYNC_ALU_STALL_SIMD1_PIX = 78,
> + SQ_SYNC_ALU_STALL_SIMD2_PIX = 79,
> + SQ_PERFCOUNT_PIX_POP_THREAD = 80,
> + SQ_SYNC_TEX_STALL_PIX = 81,
> + SQ_SYNC_VC_STALL_PIX = 82,
> + SQ_CONSTANTS_USED_SIMD2 = 83,
> + SQ_CONSTANTS_SENT_SP_SIMD2 = 84,
> + SQ_PERFCOUNT_VTX_DEALLOC_ACK = 85,
> + SQ_PERFCOUNT_PIX_DEALLOC_ACK = 86,
> + SQ_ALU0_FIFO_FULL_SIMD0 = 87,
> + SQ_ALU1_FIFO_FULL_SIMD0 = 88,
> + SQ_ALU0_FIFO_FULL_SIMD1 = 89,
> + SQ_ALU1_FIFO_FULL_SIMD1 = 90,
> + SQ_ALU0_FIFO_FULL_SIMD2 = 91,
> + SQ_ALU1_FIFO_FULL_SIMD2 = 92,
> + SQ_ALU0_FIFO_FULL_SIMD3 = 93,
> + SQ_ALU1_FIFO_FULL_SIMD3 = 94,
> + VC_PERF_STATIC = 95,
> + VC_PERF_STALLED = 96,
> + VC_PERF_STARVED = 97,
> + VC_PERF_SEND = 98,
> + VC_PERF_ACTUAL_STARVED = 99,
> + PIXEL_THREAD_0_ACTIVE = 100,
> + VERTEX_THREAD_0_ACTIVE = 101,
> + PIXEL_THREAD_0_NUMBER = 102,
> + VERTEX_THREAD_0_NUMBER = 103,
> + VERTEX_EVENT_NUMBER = 104,
> + PIXEL_EVENT_NUMBER = 105,
> + PTRBUFF_EF_PUSH = 106,
> + PTRBUFF_EF_POP_EVENT = 107,
> + PTRBUFF_EF_POP_NEW_VTX = 108,
> + PTRBUFF_EF_POP_DEALLOC = 109,
> + PTRBUFF_EF_POP_PVECTOR = 110,
> + PTRBUFF_EF_POP_PVECTOR_X = 111,
> + PTRBUFF_EF_POP_PVECTOR_VNZ = 112,
> + PTRBUFF_PB_DEALLOC = 113,
> + PTRBUFF_PI_STATE_PPB_POP = 114,
> + PTRBUFF_PI_RTR = 115,
> + PTRBUFF_PI_READ_EN = 116,
> + PTRBUFF_PI_BUFF_SWAP = 117,
> + PTRBUFF_SQ_FREE_BUFF = 118,
> + PTRBUFF_SQ_DEC = 119,
> + PTRBUFF_SC_VALID_CNTL_EVENT = 120,
> + PTRBUFF_SC_VALID_IJ_XFER = 121,
> + PTRBUFF_SC_NEW_VECTOR_1_Q = 122,
> + PTRBUFF_QUAL_NEW_VECTOR = 123,
> + PTRBUFF_QUAL_EVENT = 124,
> + PTRBUFF_END_BUFFER = 125,
> + PTRBUFF_FILL_QUAD = 126,
> + VERTS_WRITTEN_SPI = 127,
> + TP_FETCH_INSTR_EXEC = 128,
> + TP_FETCH_INSTR_REQ = 129,
> + TP_DATA_RETURN = 130,
> + SPI_WRITE_CYCLES_SP = 131,
> + SPI_WRITES_SP = 132,
> + SP_ALU_INSTR_EXEC = 133,
> + SP_CONST_ADDR_TO_SQ = 134,
> + SP_PRED_KILLS_TO_SQ = 135,
> + SP_EXPORT_CYCLES_TO_SX = 136,
> + SP_EXPORTS_TO_SX = 137,
> + SQ_CYCLES_ELAPSED = 138,
> + SQ_TCFS_OPT_ALLOC_EXEC = 139,
> + SQ_TCFS_NO_OPT_ALLOC = 140,
> + SQ_ALU0_NO_OPT_ALLOC = 141,
> + SQ_ALU1_NO_OPT_ALLOC = 142,
> + SQ_TCFS_ARB_XFC_CNT = 143,
> + SQ_ALU0_ARB_XFC_CNT = 144,
> + SQ_ALU1_ARB_XFC_CNT = 145,
> + SQ_TCFS_CFS_UPDATE_CNT = 146,
> + SQ_ALU0_CFS_UPDATE_CNT = 147,
> + SQ_ALU1_CFS_UPDATE_CNT = 148,
> + SQ_VTX_PUSH_THREAD_CNT = 149,
> + SQ_VTX_POP_THREAD_CNT = 150,
> + SQ_PIX_PUSH_THREAD_CNT = 151,
> + SQ_PIX_POP_THREAD_CNT = 152,
> + SQ_PIX_TOTAL = 153,
> + SQ_PIX_KILLED = 154,
> +};
> +
> +enum a2xx_sx_perfcnt_select {
> + SX_EXPORT_VECTORS = 0,
> + SX_DUMMY_QUADS = 1,
> + SX_ALPHA_FAIL = 2,
> + SX_RB_QUAD_BUSY = 3,
> + SX_RB_COLOR_BUSY = 4,
> + SX_RB_QUAD_STALL = 5,
> + SX_RB_COLOR_STALL = 6,
> +};
> +
> +enum a2xx_rbbm_perfcount1_sel {
> + RBBM1_COUNT = 0,
> + RBBM1_NRT_BUSY = 1,
> + RBBM1_RB_BUSY = 2,
> + RBBM1_SQ_CNTX0_BUSY = 3,
> + RBBM1_SQ_CNTX17_BUSY = 4,
> + RBBM1_VGT_BUSY = 5,
> + RBBM1_VGT_NODMA_BUSY = 6,
> + RBBM1_PA_BUSY = 7,
> + RBBM1_SC_CNTX_BUSY = 8,
> + RBBM1_TPC_BUSY = 9,
> + RBBM1_TC_BUSY = 10,
> + RBBM1_SX_BUSY = 11,
> + RBBM1_CP_COHER_BUSY = 12,
> + RBBM1_CP_NRT_BUSY = 13,
> + RBBM1_GFX_IDLE_STALL = 14,
> + RBBM1_INTERRUPT = 15,
> +};
> +
> +enum a2xx_cp_perfcount_sel {
> + ALWAYS_COUNT = 0,
> + TRANS_FIFO_FULL = 1,
> + TRANS_FIFO_AF = 2,
> + RCIU_PFPTRANS_WAIT = 3,
> + RCIU_NRTTRANS_WAIT = 6,
> + CSF_NRT_READ_WAIT = 8,
> + CSF_I1_FIFO_FULL = 9,
> + CSF_I2_FIFO_FULL = 10,
> + CSF_ST_FIFO_FULL = 11,
> + CSF_RING_ROQ_FULL = 13,
> + CSF_I1_ROQ_FULL = 14,
> + CSF_I2_ROQ_FULL = 15,
> + CSF_ST_ROQ_FULL = 16,
> + MIU_TAG_MEM_FULL = 18,
> + MIU_WRITECLEAN = 19,
> + MIU_NRT_WRITE_STALLED = 22,
> + MIU_NRT_READ_STALLED = 23,
> + ME_WRITE_CONFIRM_FIFO_FULL = 24,
> + ME_VS_DEALLOC_FIFO_FULL = 25,
> + ME_PS_DEALLOC_FIFO_FULL = 26,
> + ME_REGS_VS_EVENT_FIFO_FULL = 27,
> + ME_REGS_PS_EVENT_FIFO_FULL = 28,
> + ME_REGS_CF_EVENT_FIFO_FULL = 29,
> + ME_MICRO_RB_STARVED = 30,
> + ME_MICRO_I1_STARVED = 31,
> + ME_MICRO_I2_STARVED = 32,
> + ME_MICRO_ST_STARVED = 33,
> + RCIU_RBBM_DWORD_SENT = 40,
> + ME_BUSY_CLOCKS = 41,
> + ME_WAIT_CONTEXT_AVAIL = 42,
> + PFP_TYPE0_PACKET = 43,
> + PFP_TYPE3_PACKET = 44,
> + CSF_RB_WPTR_NEQ_RPTR = 45,
> + CSF_I1_SIZE_NEQ_ZERO = 46,
> + CSF_I2_SIZE_NEQ_ZERO = 47,
> + CSF_RBI1I2_FETCHING = 48,
> +};
> +
> +enum a2xx_rb_perfcnt_select {
> + RBPERF_CNTX_BUSY = 0,
> + RBPERF_CNTX_BUSY_MAX = 1,
> + RBPERF_SX_QUAD_STARVED = 2,
> + RBPERF_SX_QUAD_STARVED_MAX = 3,
> + RBPERF_GA_GC_CH0_SYS_REQ = 4,
> + RBPERF_GA_GC_CH0_SYS_REQ_MAX = 5,
> + RBPERF_GA_GC_CH1_SYS_REQ = 6,
> + RBPERF_GA_GC_CH1_SYS_REQ_MAX = 7,
> + RBPERF_MH_STARVED = 8,
> + RBPERF_MH_STARVED_MAX = 9,
> + RBPERF_AZ_BC_COLOR_BUSY = 10,
> + RBPERF_AZ_BC_COLOR_BUSY_MAX = 11,
> + RBPERF_AZ_BC_Z_BUSY = 12,
> + RBPERF_AZ_BC_Z_BUSY_MAX = 13,
> + RBPERF_RB_SC_TILE_RTR_N = 14,
> + RBPERF_RB_SC_TILE_RTR_N_MAX = 15,
> + RBPERF_RB_SC_SAMP_RTR_N = 16,
> + RBPERF_RB_SC_SAMP_RTR_N_MAX = 17,
> + RBPERF_RB_SX_QUAD_RTR_N = 18,
> + RBPERF_RB_SX_QUAD_RTR_N_MAX = 19,
> + RBPERF_RB_SX_COLOR_RTR_N = 20,
> + RBPERF_RB_SX_COLOR_RTR_N_MAX = 21,
> + RBPERF_RB_SC_SAMP_LZ_BUSY = 22,
> + RBPERF_RB_SC_SAMP_LZ_BUSY_MAX = 23,
> + RBPERF_ZXP_STALL = 24,
> + RBPERF_ZXP_STALL_MAX = 25,
> + RBPERF_EVENT_PENDING = 26,
> + RBPERF_EVENT_PENDING_MAX = 27,
> + RBPERF_RB_MH_VALID = 28,
> + RBPERF_RB_MH_VALID_MAX = 29,
> + RBPERF_SX_RB_QUAD_SEND = 30,
> + RBPERF_SX_RB_COLOR_SEND = 31,
> + RBPERF_SC_RB_TILE_SEND = 32,
> + RBPERF_SC_RB_SAMPLE_SEND = 33,
> + RBPERF_SX_RB_MEM_EXPORT = 34,
> + RBPERF_SX_RB_QUAD_EVENT = 35,
> + RBPERF_SC_RB_TILE_EVENT_FILTERED = 36,
> + RBPERF_SC_RB_TILE_EVENT_ALL = 37,
> + RBPERF_RB_SC_EZ_SEND = 38,
> + RBPERF_RB_SX_INDEX_SEND = 39,
> + RBPERF_GMEM_INTFO_RD = 40,
> + RBPERF_GMEM_INTF1_RD = 41,
> + RBPERF_GMEM_INTFO_WR = 42,
> + RBPERF_GMEM_INTF1_WR = 43,
> + RBPERF_RB_CP_CONTEXT_DONE = 44,
> + RBPERF_RB_CP_CACHE_FLUSH = 45,
> + RBPERF_ZPASS_DONE = 46,
> + RBPERF_ZCMD_VALID = 47,
> + RBPERF_CCMD_VALID = 48,
> + RBPERF_ACCUM_GRANT = 49,
> + RBPERF_ACCUM_C0_GRANT = 50,
> + RBPERF_ACCUM_C1_GRANT = 51,
> + RBPERF_ACCUM_FULL_BE_WR = 52,
> + RBPERF_ACCUM_REQUEST_NO_GRANT = 53,
> + RBPERF_ACCUM_TIMEOUT_PULSE = 54,
> + RBPERF_ACCUM_LIN_TIMEOUT_PULSE = 55,
> + RBPERF_ACCUM_CAM_HIT_FLUSHING = 56,
> +};
> +
> +enum a2xx_mh_perfcnt_select {
> + CP_R0_REQUESTS = 0,
> + CP_R1_REQUESTS = 1,
> + CP_R2_REQUESTS = 2,
> + CP_R3_REQUESTS = 3,
> + CP_R4_REQUESTS = 4,
> + CP_TOTAL_READ_REQUESTS = 5,
> + CP_TOTAL_WRITE_REQUESTS = 6,
> + CP_TOTAL_REQUESTS = 7,
> + CP_DATA_BYTES_WRITTEN = 8,
> + CP_WRITE_CLEAN_RESPONSES = 9,
> + CP_R0_READ_BURSTS_RECEIVED = 10,
> + CP_R1_READ_BURSTS_RECEIVED = 11,
> + CP_R2_READ_BURSTS_RECEIVED = 12,
> + CP_R3_READ_BURSTS_RECEIVED = 13,
> + CP_R4_READ_BURSTS_RECEIVED = 14,
> + CP_TOTAL_READ_BURSTS_RECEIVED = 15,
> + CP_R0_DATA_BEATS_READ = 16,
> + CP_R1_DATA_BEATS_READ = 17,
> + CP_R2_DATA_BEATS_READ = 18,
> + CP_R3_DATA_BEATS_READ = 19,
> + CP_R4_DATA_BEATS_READ = 20,
> + CP_TOTAL_DATA_BEATS_READ = 21,
> + VGT_R0_REQUESTS = 22,
> + VGT_R1_REQUESTS = 23,
> + VGT_TOTAL_REQUESTS = 24,
> + VGT_R0_READ_BURSTS_RECEIVED = 25,
> + VGT_R1_READ_BURSTS_RECEIVED = 26,
> + VGT_TOTAL_READ_BURSTS_RECEIVED = 27,
> + VGT_R0_DATA_BEATS_READ = 28,
> + VGT_R1_DATA_BEATS_READ = 29,
> + VGT_TOTAL_DATA_BEATS_READ = 30,
> + TC_TOTAL_REQUESTS = 31,
> + TC_ROQ_REQUESTS = 32,
> + TC_INFO_SENT = 33,
> + TC_READ_BURSTS_RECEIVED = 34,
> + TC_DATA_BEATS_READ = 35,
> + TCD_BURSTS_READ = 36,
> + RB_REQUESTS = 37,
> + RB_DATA_BYTES_WRITTEN = 38,
> + RB_WRITE_CLEAN_RESPONSES = 39,
> + AXI_READ_REQUESTS_ID_0 = 40,
> + AXI_READ_REQUESTS_ID_1 = 41,
> + AXI_READ_REQUESTS_ID_2 = 42,
> + AXI_READ_REQUESTS_ID_3 = 43,
> + AXI_READ_REQUESTS_ID_4 = 44,
> + AXI_READ_REQUESTS_ID_5 = 45,
> + AXI_READ_REQUESTS_ID_6 = 46,
> + AXI_READ_REQUESTS_ID_7 = 47,
> + AXI_TOTAL_READ_REQUESTS = 48,
> + AXI_WRITE_REQUESTS_ID_0 = 49,
> + AXI_WRITE_REQUESTS_ID_1 = 50,
> + AXI_WRITE_REQUESTS_ID_2 = 51,
> + AXI_WRITE_REQUESTS_ID_3 = 52,
> + AXI_WRITE_REQUESTS_ID_4 = 53,
> + AXI_WRITE_REQUESTS_ID_5 = 54,
> + AXI_WRITE_REQUESTS_ID_6 = 55,
> + AXI_WRITE_REQUESTS_ID_7 = 56,
> + AXI_TOTAL_WRITE_REQUESTS = 57,
> + AXI_TOTAL_REQUESTS_ID_0 = 58,
> + AXI_TOTAL_REQUESTS_ID_1 = 59,
> + AXI_TOTAL_REQUESTS_ID_2 = 60,
> + AXI_TOTAL_REQUESTS_ID_3 = 61,
> + AXI_TOTAL_REQUESTS_ID_4 = 62,
> + AXI_TOTAL_REQUESTS_ID_5 = 63,
> + AXI_TOTAL_REQUESTS_ID_6 = 64,
> + AXI_TOTAL_REQUESTS_ID_7 = 65,
> + AXI_TOTAL_REQUESTS = 66,
> + AXI_READ_CHANNEL_BURSTS_ID_0 = 67,
> + AXI_READ_CHANNEL_BURSTS_ID_1 = 68,
> + AXI_READ_CHANNEL_BURSTS_ID_2 = 69,
> + AXI_READ_CHANNEL_BURSTS_ID_3 = 70,
> + AXI_READ_CHANNEL_BURSTS_ID_4 = 71,
> + AXI_READ_CHANNEL_BURSTS_ID_5 = 72,
> + AXI_READ_CHANNEL_BURSTS_ID_6 = 73,
> + AXI_READ_CHANNEL_BURSTS_ID_7 = 74,
> + AXI_READ_CHANNEL_TOTAL_BURSTS = 75,
> + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0 = 76,
> + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1 = 77,
> + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2 = 78,
> + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3 = 79,
> + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4 = 80,
> + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5 = 81,
> + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6 = 82,
> + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7 = 83,
> + AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ = 84,
> + AXI_WRITE_CHANNEL_BURSTS_ID_0 = 85,
> + AXI_WRITE_CHANNEL_BURSTS_ID_1 = 86,
> + AXI_WRITE_CHANNEL_BURSTS_ID_2 = 87,
> + AXI_WRITE_CHANNEL_BURSTS_ID_3 = 88,
> + AXI_WRITE_CHANNEL_BURSTS_ID_4 = 89,
> + AXI_WRITE_CHANNEL_BURSTS_ID_5 = 90,
> + AXI_WRITE_CHANNEL_BURSTS_ID_6 = 91,
> + AXI_WRITE_CHANNEL_BURSTS_ID_7 = 92,
> + AXI_WRITE_CHANNEL_TOTAL_BURSTS = 93,
> + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0 = 94,
> + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1 = 95,
> + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2 = 96,
> + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3 = 97,
> + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4 = 98,
> + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5 = 99,
> + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6 = 100,
> + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7 = 101,
> + AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN = 102,
> + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0 = 103,
> + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1 = 104,
> + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2 = 105,
> + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3 = 106,
> + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4 = 107,
> + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5 = 108,
> + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6 = 109,
> + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7 = 110,
> + AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES = 111,
> + TOTAL_MMU_MISSES = 112,
> + MMU_READ_MISSES = 113,
> + MMU_WRITE_MISSES = 114,
> + TOTAL_MMU_HITS = 115,
> + MMU_READ_HITS = 116,
> + MMU_WRITE_HITS = 117,
> + SPLIT_MODE_TC_HITS = 118,
> + SPLIT_MODE_TC_MISSES = 119,
> + SPLIT_MODE_NON_TC_HITS = 120,
> + SPLIT_MODE_NON_TC_MISSES = 121,
> + STALL_AWAITING_TLB_MISS_FETCH = 122,
> + MMU_TLB_MISS_READ_BURSTS_RECEIVED = 123,
> + MMU_TLB_MISS_DATA_BEATS_READ = 124,
> + CP_CYCLES_HELD_OFF = 125,
> + VGT_CYCLES_HELD_OFF = 126,
> + TC_CYCLES_HELD_OFF = 127,
> + TC_ROQ_CYCLES_HELD_OFF = 128,
> + TC_CYCLES_HELD_OFF_TCD_FULL = 129,
> + RB_CYCLES_HELD_OFF = 130,
> + TOTAL_CYCLES_ANY_CLNT_HELD_OFF = 131,
> + TLB_MISS_CYCLES_HELD_OFF = 132,
> + AXI_READ_REQUEST_HELD_OFF = 133,
> + AXI_WRITE_REQUEST_HELD_OFF = 134,
> + AXI_REQUEST_HELD_OFF = 135,
> + AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT = 136,
> + AXI_WRITE_DATA_HELD_OFF = 137,
> + CP_SAME_PAGE_BANK_REQUESTS = 138,
> + VGT_SAME_PAGE_BANK_REQUESTS = 139,
> + TC_SAME_PAGE_BANK_REQUESTS = 140,
> + TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS = 141,
> + RB_SAME_PAGE_BANK_REQUESTS = 142,
> + TOTAL_SAME_PAGE_BANK_REQUESTS = 143,
> + CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 144,
> + VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 145,
> + TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 146,
> + RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 147,
> + TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT = 148,
> + TOTAL_MH_READ_REQUESTS = 149,
> + TOTAL_MH_WRITE_REQUESTS = 150,
> + TOTAL_MH_REQUESTS = 151,
> + MH_BUSY = 152,
> + CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 153,
> + VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 154,
> + TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 155,
> + RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 156,
> + TC_ROQ_N_VALID_ENTRIES = 157,
> + ARQ_N_ENTRIES = 158,
> + WDB_N_ENTRIES = 159,
> + MH_READ_LATENCY_OUTST_REQ_SUM = 160,
> + MC_READ_LATENCY_OUTST_REQ_SUM = 161,
> + MC_TOTAL_READ_REQUESTS = 162,
> + ELAPSED_CYCLES_MH_GATED_CLK = 163,
> + ELAPSED_CLK_CYCLES = 164,
> + CP_W_16B_REQUESTS = 165,
> + CP_W_32B_REQUESTS = 166,
> + TC_16B_REQUESTS = 167,
> + TC_32B_REQUESTS = 168,
> + PA_REQUESTS = 169,
> + PA_DATA_BYTES_WRITTEN = 170,
> + PA_WRITE_CLEAN_RESPONSES = 171,
> + PA_CYCLES_HELD_OFF = 172,
> + AXI_READ_REQUEST_DATA_BEATS_ID_0 = 173,
> + AXI_READ_REQUEST_DATA_BEATS_ID_1 = 174,
> + AXI_READ_REQUEST_DATA_BEATS_ID_2 = 175,
> + AXI_READ_REQUEST_DATA_BEATS_ID_3 = 176,
> + AXI_READ_REQUEST_DATA_BEATS_ID_4 = 177,
> + AXI_READ_REQUEST_DATA_BEATS_ID_5 = 178,
> + AXI_READ_REQUEST_DATA_BEATS_ID_6 = 179,
> + AXI_READ_REQUEST_DATA_BEATS_ID_7 = 180,
> + AXI_TOTAL_READ_REQUEST_DATA_BEATS = 181,
> +};
> +
> enum adreno_mmu_clnt_beh {
> BEH_NEVR = 0,
> BEH_TRAN_RNG = 1,
> @@ -268,9 +1118,9 @@ enum sq_tex_border_color {
> };
>
> enum sq_tex_sign {
> - SQ_TEX_SIGN_UNISIGNED = 0,
> + SQ_TEX_SIGN_UNSIGNED = 0,
> SQ_TEX_SIGN_SIGNED = 1,
> - SQ_TEX_SIGN_UNISIGNED_BIASED = 2,
> + SQ_TEX_SIGN_UNSIGNED_BIASED = 2,
> SQ_TEX_SIGN_GAMMA = 3,
> };
>
> @@ -1842,6 +2692,10 @@ static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val)
>
> #define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE 0x00002380
>
> +#define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_OFFSET 0x00002381
> +
> +#define REG_A2XX_PA_SU_POLY_OFFSET_BACK_SCALE 0x00002382
> +
> #define REG_A2XX_PA_SU_POLY_OFFSET_BACK_OFFSET 0x00002383
>
> #define REG_A2XX_SQ_CONSTANT_0 0x00004000
> @@ -1858,6 +2712,220 @@ static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val)
>
> #define REG_A2XX_COHER_STATUS_PM4 0x00000a2b
>
> +#define REG_A2XX_PA_SU_PERFCOUNTER0_SELECT 0x00000c88
> +
> +#define REG_A2XX_PA_SU_PERFCOUNTER1_SELECT 0x00000c89
> +
> +#define REG_A2XX_PA_SU_PERFCOUNTER2_SELECT 0x00000c8a
> +
> +#define REG_A2XX_PA_SU_PERFCOUNTER3_SELECT 0x00000c8b
> +
> +#define REG_A2XX_PA_SU_PERFCOUNTER0_LOW 0x00000c8c
> +
> +#define REG_A2XX_PA_SU_PERFCOUNTER0_HI 0x00000c8d
> +
> +#define REG_A2XX_PA_SU_PERFCOUNTER1_LOW 0x00000c8e
> +
> +#define REG_A2XX_PA_SU_PERFCOUNTER1_HI 0x00000c8f
> +
> +#define REG_A2XX_PA_SU_PERFCOUNTER2_LOW 0x00000c90
> +
> +#define REG_A2XX_PA_SU_PERFCOUNTER2_HI 0x00000c91
> +
> +#define REG_A2XX_PA_SU_PERFCOUNTER3_LOW 0x00000c92
> +
> +#define REG_A2XX_PA_SU_PERFCOUNTER3_HI 0x00000c93
> +
> +#define REG_A2XX_PA_SC_PERFCOUNTER0_SELECT 0x00000c98
> +
> +#define REG_A2XX_PA_SC_PERFCOUNTER0_LOW 0x00000c99
> +
> +#define REG_A2XX_PA_SC_PERFCOUNTER0_HI 0x00000c9a
> +
> +#define REG_A2XX_VGT_PERFCOUNTER0_SELECT 0x00000c48
> +
> +#define REG_A2XX_VGT_PERFCOUNTER1_SELECT 0x00000c49
> +
> +#define REG_A2XX_VGT_PERFCOUNTER2_SELECT 0x00000c4a
> +
> +#define REG_A2XX_VGT_PERFCOUNTER3_SELECT 0x00000c4b
> +
> +#define REG_A2XX_VGT_PERFCOUNTER0_LOW 0x00000c4c
> +
> +#define REG_A2XX_VGT_PERFCOUNTER1_LOW 0x00000c4e
> +
> +#define REG_A2XX_VGT_PERFCOUNTER2_LOW 0x00000c50
> +
> +#define REG_A2XX_VGT_PERFCOUNTER3_LOW 0x00000c52
> +
> +#define REG_A2XX_VGT_PERFCOUNTER0_HI 0x00000c4d
> +
> +#define REG_A2XX_VGT_PERFCOUNTER1_HI 0x00000c4f
> +
> +#define REG_A2XX_VGT_PERFCOUNTER2_HI 0x00000c51
> +
> +#define REG_A2XX_VGT_PERFCOUNTER3_HI 0x00000c53
> +
> +#define REG_A2XX_TCR_PERFCOUNTER0_SELECT 0x00000e05
> +
> +#define REG_A2XX_TCR_PERFCOUNTER1_SELECT 0x00000e08
> +
> +#define REG_A2XX_TCR_PERFCOUNTER0_HI 0x00000e06
> +
> +#define REG_A2XX_TCR_PERFCOUNTER1_HI 0x00000e09
> +
> +#define REG_A2XX_TCR_PERFCOUNTER0_LOW 0x00000e07
> +
> +#define REG_A2XX_TCR_PERFCOUNTER1_LOW 0x00000e0a
> +
> +#define REG_A2XX_TP0_PERFCOUNTER0_SELECT 0x00000e1f
> +
> +#define REG_A2XX_TP0_PERFCOUNTER0_HI 0x00000e20
> +
> +#define REG_A2XX_TP0_PERFCOUNTER0_LOW 0x00000e21
> +
> +#define REG_A2XX_TP0_PERFCOUNTER1_SELECT 0x00000e22
> +
> +#define REG_A2XX_TP0_PERFCOUNTER1_HI 0x00000e23
> +
> +#define REG_A2XX_TP0_PERFCOUNTER1_LOW 0x00000e24
> +
> +#define REG_A2XX_TCM_PERFCOUNTER0_SELECT 0x00000e54
> +
> +#define REG_A2XX_TCM_PERFCOUNTER1_SELECT 0x00000e57
> +
> +#define REG_A2XX_TCM_PERFCOUNTER0_HI 0x00000e55
> +
> +#define REG_A2XX_TCM_PERFCOUNTER1_HI 0x00000e58
> +
> +#define REG_A2XX_TCM_PERFCOUNTER0_LOW 0x00000e56
> +
> +#define REG_A2XX_TCM_PERFCOUNTER1_LOW 0x00000e59
> +
> +#define REG_A2XX_TCF_PERFCOUNTER0_SELECT 0x00000e5a
> +
> +#define REG_A2XX_TCF_PERFCOUNTER1_SELECT 0x00000e5d
> +
> +#define REG_A2XX_TCF_PERFCOUNTER2_SELECT 0x00000e60
> +
> +#define REG_A2XX_TCF_PERFCOUNTER3_SELECT 0x00000e63
> +
> +#define REG_A2XX_TCF_PERFCOUNTER4_SELECT 0x00000e66
> +
> +#define REG_A2XX_TCF_PERFCOUNTER5_SELECT 0x00000e69
> +
> +#define REG_A2XX_TCF_PERFCOUNTER6_SELECT 0x00000e6c
> +
> +#define REG_A2XX_TCF_PERFCOUNTER7_SELECT 0x00000e6f
> +
> +#define REG_A2XX_TCF_PERFCOUNTER8_SELECT 0x00000e72
> +
> +#define REG_A2XX_TCF_PERFCOUNTER9_SELECT 0x00000e75
> +
> +#define REG_A2XX_TCF_PERFCOUNTER10_SELECT 0x00000e78
> +
> +#define REG_A2XX_TCF_PERFCOUNTER11_SELECT 0x00000e7b
> +
> +#define REG_A2XX_TCF_PERFCOUNTER0_HI 0x00000e5b
> +
> +#define REG_A2XX_TCF_PERFCOUNTER1_HI 0x00000e5e
> +
> +#define REG_A2XX_TCF_PERFCOUNTER2_HI 0x00000e61
> +
> +#define REG_A2XX_TCF_PERFCOUNTER3_HI 0x00000e64
> +
> +#define REG_A2XX_TCF_PERFCOUNTER4_HI 0x00000e67
> +
> +#define REG_A2XX_TCF_PERFCOUNTER5_HI 0x00000e6a
> +
> +#define REG_A2XX_TCF_PERFCOUNTER6_HI 0x00000e6d
> +
> +#define REG_A2XX_TCF_PERFCOUNTER7_HI 0x00000e70
> +
> +#define REG_A2XX_TCF_PERFCOUNTER8_HI 0x00000e73
> +
> +#define REG_A2XX_TCF_PERFCOUNTER9_HI 0x00000e76
> +
> +#define REG_A2XX_TCF_PERFCOUNTER10_HI 0x00000e79
> +
> +#define REG_A2XX_TCF_PERFCOUNTER11_HI 0x00000e7c
> +
> +#define REG_A2XX_TCF_PERFCOUNTER0_LOW 0x00000e5c
> +
> +#define REG_A2XX_TCF_PERFCOUNTER1_LOW 0x00000e5f
> +
> +#define REG_A2XX_TCF_PERFCOUNTER2_LOW 0x00000e62
> +
> +#define REG_A2XX_TCF_PERFCOUNTER3_LOW 0x00000e65
> +
> +#define REG_A2XX_TCF_PERFCOUNTER4_LOW 0x00000e68
> +
> +#define REG_A2XX_TCF_PERFCOUNTER5_LOW 0x00000e6b
> +
> +#define REG_A2XX_TCF_PERFCOUNTER6_LOW 0x00000e6e
> +
> +#define REG_A2XX_TCF_PERFCOUNTER7_LOW 0x00000e71
> +
> +#define REG_A2XX_TCF_PERFCOUNTER8_LOW 0x00000e74
> +
> +#define REG_A2XX_TCF_PERFCOUNTER9_LOW 0x00000e77
> +
> +#define REG_A2XX_TCF_PERFCOUNTER10_LOW 0x00000e7a
> +
> +#define REG_A2XX_TCF_PERFCOUNTER11_LOW 0x00000e7d
> +
> +#define REG_A2XX_SQ_PERFCOUNTER0_SELECT 0x00000dc8
> +
> +#define REG_A2XX_SQ_PERFCOUNTER1_SELECT 0x00000dc9
> +
> +#define REG_A2XX_SQ_PERFCOUNTER2_SELECT 0x00000dca
> +
> +#define REG_A2XX_SQ_PERFCOUNTER3_SELECT 0x00000dcb
> +
> +#define REG_A2XX_SQ_PERFCOUNTER0_LOW 0x00000dcc
> +
> +#define REG_A2XX_SQ_PERFCOUNTER0_HI 0x00000dcd
> +
> +#define REG_A2XX_SQ_PERFCOUNTER1_LOW 0x00000dce
> +
> +#define REG_A2XX_SQ_PERFCOUNTER1_HI 0x00000dcf
> +
> +#define REG_A2XX_SQ_PERFCOUNTER2_LOW 0x00000dd0
> +
> +#define REG_A2XX_SQ_PERFCOUNTER2_HI 0x00000dd1
> +
> +#define REG_A2XX_SQ_PERFCOUNTER3_LOW 0x00000dd2
> +
> +#define REG_A2XX_SQ_PERFCOUNTER3_HI 0x00000dd3
> +
> +#define REG_A2XX_SX_PERFCOUNTER0_SELECT 0x00000dd4
> +
> +#define REG_A2XX_SX_PERFCOUNTER0_LOW 0x00000dd8
> +
> +#define REG_A2XX_SX_PERFCOUNTER0_HI 0x00000dd9
> +
> +#define REG_A2XX_MH_PERFCOUNTER0_SELECT 0x00000a46
> +
> +#define REG_A2XX_MH_PERFCOUNTER1_SELECT 0x00000a4a
> +
> +#define REG_A2XX_MH_PERFCOUNTER0_CONFIG 0x00000a47
> +
> +#define REG_A2XX_MH_PERFCOUNTER1_CONFIG 0x00000a4b
> +
> +#define REG_A2XX_MH_PERFCOUNTER0_LOW 0x00000a48
> +
> +#define REG_A2XX_MH_PERFCOUNTER1_LOW 0x00000a4c
> +
> +#define REG_A2XX_MH_PERFCOUNTER0_HI 0x00000a49
> +
> +#define REG_A2XX_MH_PERFCOUNTER1_HI 0x00000a4d
> +
> +#define REG_A2XX_RB_PERFCOUNTER0_SELECT 0x00000f04
> +
> +#define REG_A2XX_RB_PERFCOUNTER0_LOW 0x00000f08
> +
> +#define REG_A2XX_RB_PERFCOUNTER0_HI 0x00000f09
> +
> #define REG_A2XX_SQ_TEX_0 0x00000000
> #define A2XX_SQ_TEX_0_TYPE__MASK 0x00000003
> #define A2XX_SQ_TEX_0_TYPE__SHIFT 0
> @@ -1913,7 +2981,7 @@ static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val)
> {
> return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK;
> }
> -#define A2XX_SQ_TEX_0_TILED 0x00000002
> +#define A2XX_SQ_TEX_0_TILED 0x80000000
>
> #define REG_A2XX_SQ_TEX_1 0x00000001
> #define A2XX_SQ_TEX_1_FORMAT__MASK 0x0000003f
> @@ -2001,7 +3069,7 @@ static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val)
> }
> #define A2XX_SQ_TEX_3_EXP_ADJUST__MASK 0x0007e000
> #define A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT 13
> -static inline uint32_t A2XX_SQ_TEX_3_EXP_ADJUST(uint32_t val)
> +static inline uint32_t A2XX_SQ_TEX_3_EXP_ADJUST(int32_t val)
> {
> return ((val) << A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT) & A2XX_SQ_TEX_3_EXP_ADJUST__MASK;
> }
> diff --git a/drivers/gpu/drm/msm/adreno/a3xx.xml.h b/drivers/gpu/drm/msm/adreno/a3xx.xml.h
> index 17059f242a98..88c90d31d567 100644
> --- a/drivers/gpu/drm/msm/adreno/a3xx.xml.h
> +++ b/drivers/gpu/drm/msm/adreno/a3xx.xml.h
> @@ -8,19 +8,21 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
> git clone https://github.com/freedreno/envytools.git
>
> The rules-ng-ng source files this header was generated from are:
> -- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 42463 bytes, from 2018-11-19 13:44:03)
> -- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14201 bytes, from 2018-12-02 17:29:54)
> -- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43052 bytes, from 2018-12-02 17:29:54)
> -- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-02 17:29:54)
> -- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 140790 bytes, from 2018-12-02 17:29:54)
> -- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
> -- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
> -
> -Copyright (C) 2013-2018 by the following authors:
> +- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-06-21 22:29:16)
> +- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
> +- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 89649 bytes, from 2020-07-04 19:55:04)
> +- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14239 bytes, from 2020-07-04 19:55:04)
> +- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 63258 bytes, from 2020-07-07 19:26:50)
> +- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84246 bytes, from 2020-07-04 19:55:04)
> +- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112247 bytes, from 2020-07-04 19:55:04)
> +- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 148499 bytes, from 2020-07-04 20:00:49)
> +- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 174474 bytes, from 2020-07-04 20:56:59)
> +- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10768 bytes, from 2020-05-20 19:42:03)
> +- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
> +- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-06-21 22:29:16)
> +- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-06-21 22:29:43)
> +
> +Copyright (C) 2013-2020 by the following authors:
> - Rob Clark <robdclark@gmail.com> (robclark)
> - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
>
> @@ -48,7 +50,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>
> enum a3xx_tile_mode {
> LINEAR = 0,
> + TILE_4X4 = 1,
> TILE_32X32 = 2,
> + TILE_4X2 = 3,
> };
>
> enum a3xx_state_block_id {
> @@ -123,6 +127,7 @@ enum a3xx_vtx_fmt {
> VFMT_2_10_10_10_UNORM = 61,
> VFMT_2_10_10_10_SINT = 62,
> VFMT_2_10_10_10_SNORM = 63,
> + VFMT_NONE = 255,
> };
>
> enum a3xx_tex_fmt {
> @@ -206,6 +211,7 @@ enum a3xx_tex_fmt {
> TFMT_ETC2_RGBA8 = 116,
> TFMT_ETC2_RGB8A1 = 117,
> TFMT_ETC2_RGB8 = 118,
> + TFMT_NONE = 255,
> };
>
> enum a3xx_tex_fetchsize {
> @@ -228,8 +234,8 @@ enum a3xx_color_fmt {
> RB_R8G8B8A8_SINT = 11,
> RB_R8G8_UNORM = 12,
> RB_R8G8_SNORM = 13,
> - RB_R8_UINT = 14,
> - RB_R8_SINT = 15,
> + RB_R8G8_UINT = 14,
> + RB_R8G8_SINT = 15,
> RB_R10G10B10A2_UNORM = 16,
> RB_A2R10G10B10_UNORM = 17,
> RB_R10G10B10A2_UINT = 18,
> @@ -261,6 +267,7 @@ enum a3xx_color_fmt {
> RB_R32_UINT = 56,
> RB_R32G32_UINT = 57,
> RB_R32G32B32A32_UINT = 59,
> + RB_NONE = 255,
> };
>
> enum a3xx_cp_perfcounter_select {
> @@ -932,6 +939,9 @@ static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460
>
> #define REG_A3XX_GRAS_CL_CLIP_CNTL 0x00002040
> #define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER 0x00001000
> +#define A3XX_GRAS_CL_CLIP_CNTL_IJ_NON_PERSP_CENTER 0x00002000
> +#define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTROID 0x00004000
> +#define A3XX_GRAS_CL_CLIP_CNTL_IJ_NON_PERSP_CENTROID 0x00008000
> #define A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000
> #define A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000
> #define A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE 0x00080000
> @@ -1170,10 +1180,12 @@ static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val)
> }
> #define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00001000
> #define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM 0x00002000
> -#define A3XX_RB_RENDER_CONTROL_XCOORD 0x00004000
> -#define A3XX_RB_RENDER_CONTROL_YCOORD 0x00008000
> -#define A3XX_RB_RENDER_CONTROL_ZCOORD 0x00010000
> -#define A3XX_RB_RENDER_CONTROL_WCOORD 0x00020000
> +#define A3XX_RB_RENDER_CONTROL_COORD_MASK__MASK 0x0003c000
> +#define A3XX_RB_RENDER_CONTROL_COORD_MASK__SHIFT 14
> +static inline uint32_t A3XX_RB_RENDER_CONTROL_COORD_MASK(uint32_t val)
> +{
> + return ((val) << A3XX_RB_RENDER_CONTROL_COORD_MASK__SHIFT) & A3XX_RB_RENDER_CONTROL_COORD_MASK__MASK;
> +}
> #define A3XX_RB_RENDER_CONTROL_I_CLAMP_ENABLE 0x00080000
> #define A3XX_RB_RENDER_CONTROL_COV_VALUE_OUTPUT_ENABLE 0x00100000
> #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST 0x00400000
> @@ -1755,11 +1767,29 @@ static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
> }
>
> #define REG_A3XX_HLSQ_CONTROL_3_REG 0x00002203
> -#define A3XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff
> -#define A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0
> -static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val)
> +#define A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID__MASK 0x000000ff
> +#define A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID__SHIFT 0
> +static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID(uint32_t val)
> +{
> + return ((val) << A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID__MASK;
> +}
> +#define A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID__MASK 0x0000ff00
> +#define A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID__SHIFT 8
> +static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID(uint32_t val)
> +{
> + return ((val) << A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID__MASK;
> +}
> +#define A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID__MASK 0x00ff0000
> +#define A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID__SHIFT 16
> +static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID(uint32_t val)
> {
> - return ((val) << A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_REGID__MASK;
> + return ((val) << A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID__MASK;
> +}
> +#define A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID__MASK 0xff000000
> +#define A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID__SHIFT 24
> +static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID(uint32_t val)
> +{
> + return ((val) << A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID__MASK;
> }
>
> #define REG_A3XX_HLSQ_VS_CONTROL_REG 0x00002204
> @@ -1944,8 +1974,6 @@ static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
>
> #define REG_A3XX_VFD_INDEX_OFFSET 0x00002245
>
> -#define REG_A3XX_VFD_INDEX_OFFSET 0x00002245
> -
> static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0) { return 0x00002246 + 0x2*i0; }
>
> static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x00002246 + 0x2*i0; }
> @@ -3107,7 +3135,12 @@ static inline uint32_t A3XX_TEX_SAMP_1_MIN_LOD(float val)
> }
>
> #define REG_A3XX_TEX_CONST_0 0x00000000
> -#define A3XX_TEX_CONST_0_TILED 0x00000001
> +#define A3XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003
> +#define A3XX_TEX_CONST_0_TILE_MODE__SHIFT 0
> +static inline uint32_t A3XX_TEX_CONST_0_TILE_MODE(enum a3xx_tile_mode val)
> +{
> + return ((val) << A3XX_TEX_CONST_0_TILE_MODE__SHIFT) & A3XX_TEX_CONST_0_TILE_MODE__MASK;
> +}
> #define A3XX_TEX_CONST_0_SRGB 0x00000004
> #define A3XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
> #define A3XX_TEX_CONST_0_SWIZ_X__SHIFT 4
> diff --git a/drivers/gpu/drm/msm/adreno/a4xx.xml.h b/drivers/gpu/drm/msm/adreno/a4xx.xml.h
> index 9b51e25a9583..b21deffcbf2e 100644
> --- a/drivers/gpu/drm/msm/adreno/a4xx.xml.h
> +++ b/drivers/gpu/drm/msm/adreno/a4xx.xml.h
> @@ -8,19 +8,21 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
> git clone https://github.com/freedreno/envytools.git
>
> The rules-ng-ng source files this header was generated from are:
> -- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 42463 bytes, from 2018-11-19 13:44:03)
> -- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14201 bytes, from 2018-12-02 17:29:54)
> -- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43052 bytes, from 2018-12-02 17:29:54)
> -- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-02 17:29:54)
> -- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 140790 bytes, from 2018-12-02 17:29:54)
> -- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
> -- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
> -
> -Copyright (C) 2013-2018 by the following authors:
> +- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-06-21 22:29:16)
> +- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
> +- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 89649 bytes, from 2020-07-04 19:55:04)
> +- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14239 bytes, from 2020-07-04 19:55:04)
> +- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 63258 bytes, from 2020-07-07 19:26:50)
> +- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84246 bytes, from 2020-07-04 19:55:04)
> +- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112247 bytes, from 2020-07-04 19:55:04)
> +- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 148499 bytes, from 2020-07-04 20:00:49)
> +- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 174474 bytes, from 2020-07-04 20:56:59)
> +- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10768 bytes, from 2020-05-20 19:42:03)
> +- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
> +- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-06-21 22:29:16)
> +- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-06-21 22:29:43)
> +
> +Copyright (C) 2013-2020 by the following authors:
> - Rob Clark <robdclark@gmail.com> (robclark)
> - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
>
> @@ -91,6 +93,7 @@ enum a4xx_color_fmt {
> RB4_R32G32B32A32_FLOAT = 60,
> RB4_R32G32B32A32_UINT = 61,
> RB4_R32G32B32A32_SINT = 62,
> + RB4_NONE = 255,
> };
>
> enum a4xx_tile_mode {
> @@ -161,6 +164,7 @@ enum a4xx_vtx_fmt {
> VFMT4_2_10_10_10_UNORM = 61,
> VFMT4_2_10_10_10_SINT = 62,
> VFMT4_2_10_10_10_SNORM = 63,
> + VFMT4_NONE = 255,
> };
>
> enum a4xx_tex_fmt {
> @@ -248,6 +252,7 @@ enum a4xx_tex_fmt {
> TFMT4_ASTC_10x10 = 122,
> TFMT4_ASTC_12x10 = 123,
> TFMT4_ASTC_12x12 = 124,
> + TFMT4_NONE = 255,
> };
>
> enum a4xx_tex_fetchsize {
> @@ -949,10 +954,12 @@ static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val)
> }
>
> #define REG_A4XX_RB_RENDER_CONTROL2 0x000020a3
> -#define A4XX_RB_RENDER_CONTROL2_XCOORD 0x00000001
> -#define A4XX_RB_RENDER_CONTROL2_YCOORD 0x00000002
> -#define A4XX_RB_RENDER_CONTROL2_ZCOORD 0x00000004
> -#define A4XX_RB_RENDER_CONTROL2_WCOORD 0x00000008
> +#define A4XX_RB_RENDER_CONTROL2_COORD_MASK__MASK 0x0000000f
> +#define A4XX_RB_RENDER_CONTROL2_COORD_MASK__SHIFT 0
> +static inline uint32_t A4XX_RB_RENDER_CONTROL2_COORD_MASK(uint32_t val)
> +{
> + return ((val) << A4XX_RB_RENDER_CONTROL2_COORD_MASK__SHIFT) & A4XX_RB_RENDER_CONTROL2_COORD_MASK__MASK;
> +}
> #define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK 0x00000010
> #define A4XX_RB_RENDER_CONTROL2_FACENESS 0x00000020
> #define A4XX_RB_RENDER_CONTROL2_SAMPLEID 0x00000040
> @@ -1877,10 +1884,6 @@ static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x
>
> #define REG_A4XX_RBBM_PERFCTR_TP_0_HI 0x00000115
>
> -#define REG_A4XX_RBBM_PERFCTR_TP_0_LO 0x00000114
> -
> -#define REG_A4XX_RBBM_PERFCTR_TP_0_HI 0x00000115
> -
> #define REG_A4XX_RBBM_PERFCTR_TP_1_LO 0x00000116
>
> #define REG_A4XX_RBBM_PERFCTR_TP_1_HI 0x00000117
> @@ -2061,8 +2064,6 @@ static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0)
>
> #define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1 0x0000009a
>
> -#define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168
> -
> #define REG_A4XX_RBBM_PERFCTR_CTL 0x00000170
>
> #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0 0x00000171
> @@ -3524,14 +3525,44 @@ static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val)
> }
>
> #define REG_A4XX_HLSQ_CONTROL_3_REG 0x000023c3
> -#define A4XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff
> -#define A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0
> -static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val)
> +#define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff
> +#define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0
> +static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)
> +{
> + return ((val) << A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK;
> +}
> +#define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00
> +#define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8
> +static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)
> +{
> + return ((val) << A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK;
> +}
> +#define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000
> +#define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16
> +static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)
> +{
> + return ((val) << A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK;
> +}
> +#define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000
> +#define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24
> +static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)
> {
> - return ((val) << A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_REGID__MASK;
> + return ((val) << A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK;
> }
>
> -#define REG_A4XX_HLSQ_CONTROL_4_REG 0x000023c4
> +#define REG_A4XX_HLSQ_CONTROL_4_REG 0x0000b985
> +#define A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff
> +#define A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0
> +static inline uint32_t A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)
> +{
> + return ((val) << A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK;
> +}
> +#define A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00
> +#define A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8
> +static inline uint32_t A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)
> +{
> + return ((val) << A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK;
> +}
>
> #define REG_A4XX_HLSQ_VS_CONTROL_REG 0x000023c5
> #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
> diff --git a/drivers/gpu/drm/msm/adreno/a5xx.xml.h b/drivers/gpu/drm/msm/adreno/a5xx.xml.h
> index 4a61d4e72c98..6c42524993a2 100644
> --- a/drivers/gpu/drm/msm/adreno/a5xx.xml.h
> +++ b/drivers/gpu/drm/msm/adreno/a5xx.xml.h
> @@ -8,19 +8,21 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
> git clone https://github.com/freedreno/envytools.git
>
> The rules-ng-ng source files this header was generated from are:
> -- /home/ubuntu/envytools/envytools/rnndb/./adreno.xml ( 501 bytes, from 2019-05-29 01:28:15)
> -- /home/ubuntu/envytools/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2019-05-29 01:28:15)
> -- /home/ubuntu/envytools/envytools/rnndb/adreno/a2xx.xml ( 79608 bytes, from 2019-05-29 01:28:15)
> -- /home/ubuntu/envytools/envytools/rnndb/adreno/adreno_common.xml ( 14239 bytes, from 2019-05-29 01:28:15)
> -- /home/ubuntu/envytools/envytools/rnndb/adreno/adreno_pm4.xml ( 43155 bytes, from 2019-05-29 01:28:15)
> -- /home/ubuntu/envytools/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2019-05-29 01:28:15)
> -- /home/ubuntu/envytools/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2019-05-29 01:28:15)
> -- /home/ubuntu/envytools/envytools/rnndb/adreno/a5xx.xml ( 147291 bytes, from 2019-05-29 14:51:41)
> -- /home/ubuntu/envytools/envytools/rnndb/adreno/a6xx.xml ( 148461 bytes, from 2019-05-29 01:28:15)
> -- /home/ubuntu/envytools/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2019-05-29 01:28:15)
> -- /home/ubuntu/envytools/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2019-05-29 01:28:15)
> -
> -Copyright (C) 2013-2019 by the following authors:
> +- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-06-21 22:29:16)
> +- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
> +- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 89649 bytes, from 2020-07-04 19:55:04)
> +- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14239 bytes, from 2020-07-04 19:55:04)
> +- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 63258 bytes, from 2020-07-07 19:26:50)
> +- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84246 bytes, from 2020-07-04 19:55:04)
> +- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112247 bytes, from 2020-07-04 19:55:04)
> +- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 148499 bytes, from 2020-07-04 20:00:49)
> +- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 174474 bytes, from 2020-07-04 20:56:59)
> +- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10768 bytes, from 2020-05-20 19:42:03)
> +- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
> +- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-06-21 22:29:16)
> +- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-06-21 22:29:43)
> +
> +Copyright (C) 2013-2020 by the following authors:
> - Rob Clark <robdclark@gmail.com> (robclark)
> - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
>
> @@ -91,6 +93,7 @@ enum a5xx_color_fmt {
> RB5_R32G32B32A32_FLOAT = 130,
> RB5_R32G32B32A32_UINT = 131,
> RB5_R32G32B32A32_SINT = 132,
> + RB5_NONE = 255,
> };
>
> enum a5xx_tile_mode {
> @@ -165,6 +168,7 @@ enum a5xx_vtx_fmt {
> VFMT5_32_32_32_32_UINT = 131,
> VFMT5_32_32_32_32_SINT = 132,
> VFMT5_32_32_32_32_FIXED = 133,
> + VFMT5_NONE = 255,
> };
>
> enum a5xx_tex_fmt {
> @@ -250,6 +254,7 @@ enum a5xx_tex_fmt {
> TFMT5_ASTC_10x10 = 204,
> TFMT5_ASTC_12x10 = 205,
> TFMT5_ASTC_12x12 = 206,
> + TFMT5_NONE = 255,
> };
>
> enum a5xx_tex_fetchsize {
> @@ -1884,14 +1889,6 @@ static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
>
> #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x0000046a
>
> -#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b
> -
> -#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c
> -
> -#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d
> -
> -#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e
> -
> #define REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000046f
>
> #define REG_A5XX_RBBM_AHB_ERROR 0x000004ed
> @@ -2455,8 +2452,6 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val)
>
> #define REG_A5XX_GPMU_PWR_COL_BINNING_CTRL 0x0000a894
>
> -#define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3
> -
> #define REG_A5XX_GPMU_WFI_CONFIG 0x0000a8c1
>
> #define REG_A5XX_GPMU_RBBM_INTR_INFO 0x0000a8d6
> @@ -2659,12 +2654,16 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val)
> #define REG_A5XX_UNKNOWN_E004 0x0000e004
>
> #define REG_A5XX_GRAS_CNTL 0x0000e005
> -#define A5XX_GRAS_CNTL_VARYING 0x00000001
> -#define A5XX_GRAS_CNTL_UNK3 0x00000008
> -#define A5XX_GRAS_CNTL_XCOORD 0x00000040
> -#define A5XX_GRAS_CNTL_YCOORD 0x00000080
> -#define A5XX_GRAS_CNTL_ZCOORD 0x00000100
> -#define A5XX_GRAS_CNTL_WCOORD 0x00000200
> +#define A5XX_GRAS_CNTL_IJ_PERSP_PIXEL 0x00000001
> +#define A5XX_GRAS_CNTL_IJ_PERSP_CENTROID 0x00000002
> +#define A5XX_GRAS_CNTL_IJ_PERSP_SAMPLE 0x00000004
> +#define A5XX_GRAS_CNTL_SIZE 0x00000008
> +#define A5XX_GRAS_CNTL_COORD_MASK__MASK 0x000003c0
> +#define A5XX_GRAS_CNTL_COORD_MASK__SHIFT 6
> +static inline uint32_t A5XX_GRAS_CNTL_COORD_MASK(uint32_t val)
> +{
> + return ((val) << A5XX_GRAS_CNTL_COORD_MASK__SHIFT) & A5XX_GRAS_CNTL_COORD_MASK__MASK;
> +}
>
> #define REG_A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x0000e006
> #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000003ff
> @@ -2991,12 +2990,16 @@ static inline uint32_t A5XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val
> #define A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
>
> #define REG_A5XX_RB_RENDER_CONTROL0 0x0000e144
> -#define A5XX_RB_RENDER_CONTROL0_VARYING 0x00000001
> -#define A5XX_RB_RENDER_CONTROL0_UNK3 0x00000008
> -#define A5XX_RB_RENDER_CONTROL0_XCOORD 0x00000040
> -#define A5XX_RB_RENDER_CONTROL0_YCOORD 0x00000080
> -#define A5XX_RB_RENDER_CONTROL0_ZCOORD 0x00000100
> -#define A5XX_RB_RENDER_CONTROL0_WCOORD 0x00000200
> +#define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL 0x00000001
> +#define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID 0x00000002
> +#define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE 0x00000004
> +#define A5XX_RB_RENDER_CONTROL0_SIZE 0x00000008
> +#define A5XX_RB_RENDER_CONTROL0_COORD_MASK__MASK 0x000003c0
> +#define A5XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT 6
> +static inline uint32_t A5XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val)
> +{
> + return ((val) << A5XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT) & A5XX_RB_RENDER_CONTROL0_COORD_MASK__MASK;
> +}
>
> #define REG_A5XX_RB_RENDER_CONTROL1 0x0000e145
> #define A5XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001
> @@ -4450,16 +4453,52 @@ static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)
> {
> return ((val) << A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK;
> }
> +#define A5XX_HLSQ_CONTROL_2_REG_SIZE__MASK 0xff000000
> +#define A5XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT 24
> +static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SIZE(uint32_t val)
> +{
> + return ((val) << A5XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_SIZE__MASK;
> +}
>
> #define REG_A5XX_HLSQ_CONTROL_3_REG 0x0000e787
> -#define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK 0x000000ff
> -#define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT 0
> -static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(uint32_t val)
> +#define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff
> +#define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0
> +static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)
> +{
> + return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK;
> +}
> +#define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00
> +#define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8
> +static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)
> +{
> + return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK;
> +}
> +#define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000
> +#define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16
> +static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)
> {
> - return ((val) << A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK;
> + return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK;
> +}
> +#define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000
> +#define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24
> +static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)
> +{
> + return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK;
> }
>
> #define REG_A5XX_HLSQ_CONTROL_4_REG 0x0000e788
> +#define A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff
> +#define A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0
> +static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)
> +{
> + return ((val) << A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK;
> +}
> +#define A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00
> +#define A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8
> +static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)
> +{
> + return ((val) << A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK;
> +}
> #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000
> #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16
> static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
> @@ -4855,10 +4894,26 @@ static inline uint32_t A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(uint32_t val)
>
> #define REG_A5XX_RB_2D_SRC_FLAGS_HI 0x00002141
>
> +#define REG_A5XX_RB_2D_SRC_FLAGS_PITCH 0x00002142
> +#define A5XX_RB_2D_SRC_FLAGS_PITCH__MASK 0xffffffff
> +#define A5XX_RB_2D_SRC_FLAGS_PITCH__SHIFT 0
> +static inline uint32_t A5XX_RB_2D_SRC_FLAGS_PITCH(uint32_t val)
> +{
> + return ((val >> 6) << A5XX_RB_2D_SRC_FLAGS_PITCH__SHIFT) & A5XX_RB_2D_SRC_FLAGS_PITCH__MASK;
> +}
> +
> #define REG_A5XX_RB_2D_DST_FLAGS_LO 0x00002143
>
> #define REG_A5XX_RB_2D_DST_FLAGS_HI 0x00002144
>
> +#define REG_A5XX_RB_2D_DST_FLAGS_PITCH 0x00002145
> +#define A5XX_RB_2D_DST_FLAGS_PITCH__MASK 0xffffffff
> +#define A5XX_RB_2D_DST_FLAGS_PITCH__SHIFT 0
> +static inline uint32_t A5XX_RB_2D_DST_FLAGS_PITCH(uint32_t val)
> +{
> + return ((val >> 6) << A5XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A5XX_RB_2D_DST_FLAGS_PITCH__MASK;
> +}
> +
> #define REG_A5XX_GRAS_2D_BLIT_CNTL 0x00002180
>
> #define REG_A5XX_GRAS_2D_SRC_INFO 0x00002181
> @@ -5085,6 +5140,13 @@ static inline uint32_t A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)
> {
> return ((val >> 12) << A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A5XX_TEX_CONST_3_ARRAY_PITCH__MASK;
> }
> +#define A5XX_TEX_CONST_3_MIN_LAYERSZ__MASK 0x07800000
> +#define A5XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT 23
> +static inline uint32_t A5XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val)
> +{
> + return ((val >> 12) << A5XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A5XX_TEX_CONST_3_MIN_LAYERSZ__MASK;
> +}
> +#define A5XX_TEX_CONST_3_TILE_ALL 0x08000000
> #define A5XX_TEX_CONST_3_FLAG 0x10000000
>
> #define REG_A5XX_TEX_CONST_4 0x00000004
> @@ -5197,5 +5259,21 @@ static inline uint32_t A5XX_SSBO_2_1_BASE_HI(uint32_t val)
> return ((val) << A5XX_SSBO_2_1_BASE_HI__SHIFT) & A5XX_SSBO_2_1_BASE_HI__MASK;
> }
>
> +#define REG_A5XX_UBO_0 0x00000000
> +#define A5XX_UBO_0_BASE_LO__MASK 0xffffffff
> +#define A5XX_UBO_0_BASE_LO__SHIFT 0
> +static inline uint32_t A5XX_UBO_0_BASE_LO(uint32_t val)
> +{
> + return ((val) << A5XX_UBO_0_BASE_LO__SHIFT) & A5XX_UBO_0_BASE_LO__MASK;
> +}
> +
> +#define REG_A5XX_UBO_1 0x00000001
> +#define A5XX_UBO_1_BASE_HI__MASK 0x0001ffff
> +#define A5XX_UBO_1_BASE_HI__SHIFT 0
> +static inline uint32_t A5XX_UBO_1_BASE_HI(uint32_t val)
> +{
> + return ((val) << A5XX_UBO_1_BASE_HI__SHIFT) & A5XX_UBO_1_BASE_HI__MASK;
> +}
> +
>
> #endif /* A5XX_XML */
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h b/drivers/gpu/drm/msm/adreno/a6xx.xml.h
> index 47840b73cdda..0e341b082db8 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h
> +++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h
> @@ -8,19 +8,21 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
> git clone https://github.com/freedreno/envytools.git
>
> The rules-ng-ng source files this header was generated from are:
> -- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 42463 bytes, from 2018-11-19 13:44:03)
> -- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14201 bytes, from 2018-12-02 17:29:54)
> -- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43052 bytes, from 2018-12-02 17:29:54)
> -- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-02 17:29:54)
> -- /home/smasetty/playarea/envytools/rnndb/adreno/a6xx.xml ( 161969 bytes, from 2019-11-29 07:18:16)
> -- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
> -- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
> -
> -Copyright (C) 2013-2019 by the following authors:
> +- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-06-21 22:29:16)
> +- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
> +- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 89649 bytes, from 2020-07-04 19:55:04)
> +- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14239 bytes, from 2020-07-04 19:55:04)
> +- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 63258 bytes, from 2020-07-07 19:26:50)
> +- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84246 bytes, from 2020-07-04 19:55:04)
> +- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112247 bytes, from 2020-07-04 19:55:04)
> +- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 148499 bytes, from 2020-07-04 20:00:49)
> +- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 174474 bytes, from 2020-07-04 20:56:59)
> +- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10768 bytes, from 2020-05-20 19:42:03)
> +- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
> +- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-06-21 22:29:16)
> +- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-06-21 22:29:43)
> +
> +Copyright (C) 2013-2020 by the following authors:
> - Rob Clark <robdclark@gmail.com> (robclark)
> - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
>
> @@ -46,219 +48,134 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
> */
>
>
> -enum a6xx_color_fmt {
> - RB6_A8_UNORM = 2,
> - RB6_R8_UNORM = 3,
> - RB6_R8_SNORM = 4,
> - RB6_R8_UINT = 5,
> - RB6_R8_SINT = 6,
> - RB6_R4G4B4A4_UNORM = 8,
> - RB6_R5G5B5A1_UNORM = 10,
> - RB6_R5G6B5_UNORM = 14,
> - RB6_R8G8_UNORM = 15,
> - RB6_R8G8_SNORM = 16,
> - RB6_R8G8_UINT = 17,
> - RB6_R8G8_SINT = 18,
> - RB6_R16_UNORM = 21,
> - RB6_R16_SNORM = 22,
> - RB6_R16_FLOAT = 23,
> - RB6_R16_UINT = 24,
> - RB6_R16_SINT = 25,
> - RB6_R8G8B8A8_UNORM = 48,
> - RB6_R8G8B8_UNORM = 49,
> - RB6_R8G8B8A8_SNORM = 50,
> - RB6_R8G8B8A8_UINT = 51,
> - RB6_R8G8B8A8_SINT = 52,
> - RB6_R10G10B10A2_UNORM = 55,
> - RB6_R10G10B10A2_UINT = 58,
> - RB6_R11G11B10_FLOAT = 66,
> - RB6_R16G16_UNORM = 67,
> - RB6_R16G16_SNORM = 68,
> - RB6_R16G16_FLOAT = 69,
> - RB6_R16G16_UINT = 70,
> - RB6_R16G16_SINT = 71,
> - RB6_R32_FLOAT = 74,
> - RB6_R32_UINT = 75,
> - RB6_R32_SINT = 76,
> - RB6_R16G16B16A16_UNORM = 96,
> - RB6_R16G16B16A16_SNORM = 97,
> - RB6_R16G16B16A16_FLOAT = 98,
> - RB6_R16G16B16A16_UINT = 99,
> - RB6_R16G16B16A16_SINT = 100,
> - RB6_R32G32_FLOAT = 103,
> - RB6_R32G32_UINT = 104,
> - RB6_R32G32_SINT = 105,
> - RB6_R32G32B32A32_FLOAT = 130,
> - RB6_R32G32B32A32_UINT = 131,
> - RB6_R32G32B32A32_SINT = 132,
> - RB6_X8Z24_UNORM = 160,
> -};
> -
> enum a6xx_tile_mode {
> TILE6_LINEAR = 0,
> TILE6_2 = 2,
> TILE6_3 = 3,
> };
>
> -enum a6xx_vtx_fmt {
> - VFMT6_8_UNORM = 3,
> - VFMT6_8_SNORM = 4,
> - VFMT6_8_UINT = 5,
> - VFMT6_8_SINT = 6,
> - VFMT6_8_8_UNORM = 15,
> - VFMT6_8_8_SNORM = 16,
> - VFMT6_8_8_UINT = 17,
> - VFMT6_8_8_SINT = 18,
> - VFMT6_16_UNORM = 21,
> - VFMT6_16_SNORM = 22,
> - VFMT6_16_FLOAT = 23,
> - VFMT6_16_UINT = 24,
> - VFMT6_16_SINT = 25,
> - VFMT6_8_8_8_UNORM = 33,
> - VFMT6_8_8_8_SNORM = 34,
> - VFMT6_8_8_8_UINT = 35,
> - VFMT6_8_8_8_SINT = 36,
> - VFMT6_8_8_8_8_UNORM = 48,
> - VFMT6_8_8_8_8_SNORM = 50,
> - VFMT6_8_8_8_8_UINT = 51,
> - VFMT6_8_8_8_8_SINT = 52,
> - VFMT6_10_10_10_2_UNORM = 54,
> - VFMT6_10_10_10_2_SNORM = 57,
> - VFMT6_10_10_10_2_UINT = 58,
> - VFMT6_10_10_10_2_SINT = 59,
> - VFMT6_11_11_10_FLOAT = 66,
> - VFMT6_16_16_UNORM = 67,
> - VFMT6_16_16_SNORM = 68,
> - VFMT6_16_16_FLOAT = 69,
> - VFMT6_16_16_UINT = 70,
> - VFMT6_16_16_SINT = 71,
> - VFMT6_32_UNORM = 72,
> - VFMT6_32_SNORM = 73,
> - VFMT6_32_FLOAT = 74,
> - VFMT6_32_UINT = 75,
> - VFMT6_32_SINT = 76,
> - VFMT6_32_FIXED = 77,
> - VFMT6_16_16_16_UNORM = 88,
> - VFMT6_16_16_16_SNORM = 89,
> - VFMT6_16_16_16_FLOAT = 90,
> - VFMT6_16_16_16_UINT = 91,
> - VFMT6_16_16_16_SINT = 92,
> - VFMT6_16_16_16_16_UNORM = 96,
> - VFMT6_16_16_16_16_SNORM = 97,
> - VFMT6_16_16_16_16_FLOAT = 98,
> - VFMT6_16_16_16_16_UINT = 99,
> - VFMT6_16_16_16_16_SINT = 100,
> - VFMT6_32_32_UNORM = 101,
> - VFMT6_32_32_SNORM = 102,
> - VFMT6_32_32_FLOAT = 103,
> - VFMT6_32_32_UINT = 104,
> - VFMT6_32_32_SINT = 105,
> - VFMT6_32_32_FIXED = 106,
> - VFMT6_32_32_32_UNORM = 112,
> - VFMT6_32_32_32_SNORM = 113,
> - VFMT6_32_32_32_UINT = 114,
> - VFMT6_32_32_32_SINT = 115,
> - VFMT6_32_32_32_FLOAT = 116,
> - VFMT6_32_32_32_FIXED = 117,
> - VFMT6_32_32_32_32_UNORM = 128,
> - VFMT6_32_32_32_32_SNORM = 129,
> - VFMT6_32_32_32_32_FLOAT = 130,
> - VFMT6_32_32_32_32_UINT = 131,
> - VFMT6_32_32_32_32_SINT = 132,
> - VFMT6_32_32_32_32_FIXED = 133,
> -};
> -
> -enum a6xx_tex_fmt {
> - TFMT6_A8_UNORM = 2,
> - TFMT6_8_UNORM = 3,
> - TFMT6_8_SNORM = 4,
> - TFMT6_8_UINT = 5,
> - TFMT6_8_SINT = 6,
> - TFMT6_4_4_4_4_UNORM = 8,
> - TFMT6_5_5_5_1_UNORM = 10,
> - TFMT6_5_6_5_UNORM = 14,
> - TFMT6_8_8_UNORM = 15,
> - TFMT6_8_8_SNORM = 16,
> - TFMT6_8_8_UINT = 17,
> - TFMT6_8_8_SINT = 18,
> - TFMT6_L8_A8_UNORM = 19,
> - TFMT6_16_UNORM = 21,
> - TFMT6_16_SNORM = 22,
> - TFMT6_16_FLOAT = 23,
> - TFMT6_16_UINT = 24,
> - TFMT6_16_SINT = 25,
> - TFMT6_8_8_8_8_UNORM = 48,
> - TFMT6_8_8_8_UNORM = 49,
> - TFMT6_8_8_8_8_SNORM = 50,
> - TFMT6_8_8_8_8_UINT = 51,
> - TFMT6_8_8_8_8_SINT = 52,
> - TFMT6_9_9_9_E5_FLOAT = 53,
> - TFMT6_10_10_10_2_UNORM = 54,
> - TFMT6_10_10_10_2_UINT = 58,
> - TFMT6_11_11_10_FLOAT = 66,
> - TFMT6_16_16_UNORM = 67,
> - TFMT6_16_16_SNORM = 68,
> - TFMT6_16_16_FLOAT = 69,
> - TFMT6_16_16_UINT = 70,
> - TFMT6_16_16_SINT = 71,
> - TFMT6_32_FLOAT = 74,
> - TFMT6_32_UINT = 75,
> - TFMT6_32_SINT = 76,
> - TFMT6_16_16_16_16_UNORM = 96,
> - TFMT6_16_16_16_16_SNORM = 97,
> - TFMT6_16_16_16_16_FLOAT = 98,
> - TFMT6_16_16_16_16_UINT = 99,
> - TFMT6_16_16_16_16_SINT = 100,
> - TFMT6_32_32_FLOAT = 103,
> - TFMT6_32_32_UINT = 104,
> - TFMT6_32_32_SINT = 105,
> - TFMT6_32_32_32_UINT = 114,
> - TFMT6_32_32_32_SINT = 115,
> - TFMT6_32_32_32_FLOAT = 116,
> - TFMT6_32_32_32_32_FLOAT = 130,
> - TFMT6_32_32_32_32_UINT = 131,
> - TFMT6_32_32_32_32_SINT = 132,
> - TFMT6_X8Z24_UNORM = 160,
> - TFMT6_ETC2_RG11_UNORM = 171,
> - TFMT6_ETC2_RG11_SNORM = 172,
> - TFMT6_ETC2_R11_UNORM = 173,
> - TFMT6_ETC2_R11_SNORM = 174,
> - TFMT6_ETC1 = 175,
> - TFMT6_ETC2_RGB8 = 176,
> - TFMT6_ETC2_RGBA8 = 177,
> - TFMT6_ETC2_RGB8A1 = 178,
> - TFMT6_DXT1 = 179,
> - TFMT6_DXT3 = 180,
> - TFMT6_DXT5 = 181,
> - TFMT6_RGTC1_UNORM = 183,
> - TFMT6_RGTC1_SNORM = 184,
> - TFMT6_RGTC2_UNORM = 187,
> - TFMT6_RGTC2_SNORM = 188,
> - TFMT6_BPTC_UFLOAT = 190,
> - TFMT6_BPTC_FLOAT = 191,
> - TFMT6_BPTC = 192,
> - TFMT6_ASTC_4x4 = 193,
> - TFMT6_ASTC_5x4 = 194,
> - TFMT6_ASTC_5x5 = 195,
> - TFMT6_ASTC_6x5 = 196,
> - TFMT6_ASTC_6x6 = 197,
> - TFMT6_ASTC_8x5 = 198,
> - TFMT6_ASTC_8x6 = 199,
> - TFMT6_ASTC_8x8 = 200,
> - TFMT6_ASTC_10x5 = 201,
> - TFMT6_ASTC_10x6 = 202,
> - TFMT6_ASTC_10x8 = 203,
> - TFMT6_ASTC_10x10 = 204,
> - TFMT6_ASTC_12x10 = 205,
> - TFMT6_ASTC_12x12 = 206,
> +enum a6xx_format {
> + FMT6_A8_UNORM = 2,
> + FMT6_8_UNORM = 3,
> + FMT6_8_SNORM = 4,
> + FMT6_8_UINT = 5,
> + FMT6_8_SINT = 6,
> + FMT6_4_4_4_4_UNORM = 8,
> + FMT6_5_5_5_1_UNORM = 10,
> + FMT6_1_5_5_5_UNORM = 12,
> + FMT6_5_6_5_UNORM = 14,
> + FMT6_8_8_UNORM = 15,
> + FMT6_8_8_SNORM = 16,
> + FMT6_8_8_UINT = 17,
> + FMT6_8_8_SINT = 18,
> + FMT6_L8_A8_UNORM = 19,
> + FMT6_16_UNORM = 21,
> + FMT6_16_SNORM = 22,
> + FMT6_16_FLOAT = 23,
> + FMT6_16_UINT = 24,
> + FMT6_16_SINT = 25,
> + FMT6_8_8_8_UNORM = 33,
> + FMT6_8_8_8_SNORM = 34,
> + FMT6_8_8_8_UINT = 35,
> + FMT6_8_8_8_SINT = 36,
> + FMT6_8_8_8_8_UNORM = 48,
> + FMT6_8_8_8_X8_UNORM = 49,
> + FMT6_8_8_8_8_SNORM = 50,
> + FMT6_8_8_8_8_UINT = 51,
> + FMT6_8_8_8_8_SINT = 52,
> + FMT6_9_9_9_E5_FLOAT = 53,
> + FMT6_10_10_10_2_UNORM = 54,
> + FMT6_10_10_10_2_UNORM_DEST = 55,
> + FMT6_10_10_10_2_SNORM = 57,
> + FMT6_10_10_10_2_UINT = 58,
> + FMT6_10_10_10_2_SINT = 59,
> + FMT6_11_11_10_FLOAT = 66,
> + FMT6_16_16_UNORM = 67,
> + FMT6_16_16_SNORM = 68,
> + FMT6_16_16_FLOAT = 69,
> + FMT6_16_16_UINT = 70,
> + FMT6_16_16_SINT = 71,
> + FMT6_32_UNORM = 72,
> + FMT6_32_SNORM = 73,
> + FMT6_32_FLOAT = 74,
> + FMT6_32_UINT = 75,
> + FMT6_32_SINT = 76,
> + FMT6_32_FIXED = 77,
> + FMT6_16_16_16_UNORM = 88,
> + FMT6_16_16_16_SNORM = 89,
> + FMT6_16_16_16_FLOAT = 90,
> + FMT6_16_16_16_UINT = 91,
> + FMT6_16_16_16_SINT = 92,
> + FMT6_16_16_16_16_UNORM = 96,
> + FMT6_16_16_16_16_SNORM = 97,
> + FMT6_16_16_16_16_FLOAT = 98,
> + FMT6_16_16_16_16_UINT = 99,
> + FMT6_16_16_16_16_SINT = 100,
> + FMT6_32_32_UNORM = 101,
> + FMT6_32_32_SNORM = 102,
> + FMT6_32_32_FLOAT = 103,
> + FMT6_32_32_UINT = 104,
> + FMT6_32_32_SINT = 105,
> + FMT6_32_32_FIXED = 106,
> + FMT6_32_32_32_UNORM = 112,
> + FMT6_32_32_32_SNORM = 113,
> + FMT6_32_32_32_UINT = 114,
> + FMT6_32_32_32_SINT = 115,
> + FMT6_32_32_32_FLOAT = 116,
> + FMT6_32_32_32_FIXED = 117,
> + FMT6_32_32_32_32_UNORM = 128,
> + FMT6_32_32_32_32_SNORM = 129,
> + FMT6_32_32_32_32_FLOAT = 130,
> + FMT6_32_32_32_32_UINT = 131,
> + FMT6_32_32_32_32_SINT = 132,
> + FMT6_32_32_32_32_FIXED = 133,
> + FMT6_G8R8B8R8_422_UNORM = 140,
> + FMT6_R8G8R8B8_422_UNORM = 141,
> + FMT6_R8_G8B8_2PLANE_420_UNORM = 142,
> + FMT6_R8_G8_B8_3PLANE_420_UNORM = 144,
> + FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 = 145,
> + FMT6_8_PLANE_UNORM = 148,
> + FMT6_Z24_UNORM_S8_UINT = 160,
> + FMT6_ETC2_RG11_UNORM = 171,
> + FMT6_ETC2_RG11_SNORM = 172,
> + FMT6_ETC2_R11_UNORM = 173,
> + FMT6_ETC2_R11_SNORM = 174,
> + FMT6_ETC1 = 175,
> + FMT6_ETC2_RGB8 = 176,
> + FMT6_ETC2_RGBA8 = 177,
> + FMT6_ETC2_RGB8A1 = 178,
> + FMT6_DXT1 = 179,
> + FMT6_DXT3 = 180,
> + FMT6_DXT5 = 181,
> + FMT6_RGTC1_UNORM = 183,
> + FMT6_RGTC1_SNORM = 184,
> + FMT6_RGTC2_UNORM = 187,
> + FMT6_RGTC2_SNORM = 188,
> + FMT6_BPTC_UFLOAT = 190,
> + FMT6_BPTC_FLOAT = 191,
> + FMT6_BPTC = 192,
> + FMT6_ASTC_4x4 = 193,
> + FMT6_ASTC_5x4 = 194,
> + FMT6_ASTC_5x5 = 195,
> + FMT6_ASTC_6x5 = 196,
> + FMT6_ASTC_6x6 = 197,
> + FMT6_ASTC_8x5 = 198,
> + FMT6_ASTC_8x6 = 199,
> + FMT6_ASTC_8x8 = 200,
> + FMT6_ASTC_10x5 = 201,
> + FMT6_ASTC_10x6 = 202,
> + FMT6_ASTC_10x8 = 203,
> + FMT6_ASTC_10x10 = 204,
> + FMT6_ASTC_12x10 = 205,
> + FMT6_ASTC_12x12 = 206,
> + FMT6_S8Z24_UINT = 234,
> + FMT6_NONE = 255,
> };
>
> -enum a6xx_tex_fetchsize {
> - TFETCH6_1_BYTE = 0,
> - TFETCH6_2_BYTE = 1,
> - TFETCH6_4_BYTE = 2,
> - TFETCH6_8_BYTE = 3,
> - TFETCH6_16_BYTE = 4,
> +enum a6xx_polygon_mode {
> + POLYMODE6_POINTS = 1,
> + POLYMODE6_LINES = 2,
> + POLYMODE6_TRIANGLES = 3,
> };
>
> enum a6xx_depth_format {
> @@ -951,10 +868,57 @@ enum a6xx_cmp_perfcounter_select {
> PERF_CMPDECMP_2D_PIXELS = 39,
> };
>
> +enum a6xx_2d_ifmt {
> + R2D_UNORM8 = 16,
> + R2D_INT32 = 7,
> + R2D_INT16 = 6,
> + R2D_INT8 = 5,
> + R2D_FLOAT32 = 4,
> + R2D_FLOAT16 = 3,
> + R2D_UNORM8_SRGB = 1,
> + R2D_RAW = 0,
> +};
> +
> +enum a6xx_ztest_mode {
> + A6XX_EARLY_Z = 0,
> + A6XX_LATE_Z = 1,
> + A6XX_EARLY_LRZ_LATE_Z = 2,
> +};
> +
> +enum a6xx_layer_type {
> + LAYER_MULTISAMPLE_ARRAY = 0,
> + LAYER_3D = 1,
> + LAYER_CUBEMAP = 2,
> + LAYER_2D_ARRAY = 3,
> +};
> +
> +enum a6xx_rotation {
> + ROTATE_0 = 0,
> + ROTATE_90 = 1,
> + ROTATE_180 = 2,
> + ROTATE_270 = 3,
> + ROTATE_HFLIP = 4,
> + ROTATE_VFLIP = 5,
> +};
> +
> +enum a6xx_tess_spacing {
> + TESS_EQUAL = 0,
> + TESS_FRACTIONAL_ODD = 2,
> + TESS_FRACTIONAL_EVEN = 3,
> +};
> +
> +enum a6xx_tess_output {
> + TESS_POINTS = 0,
> + TESS_LINES = 1,
> + TESS_CW_TRIS = 2,
> + TESS_CCW_TRIS = 3,
> +};
> +
> enum a6xx_tex_filter {
> A6XX_TEX_NEAREST = 0,
> A6XX_TEX_LINEAR = 1,
> A6XX_TEX_ANISO = 2,
> + A6XX_TEX_CUBIC = 3,
> };
>
> enum a6xx_tex_clamp {
> @@ -973,6 +937,12 @@ enum a6xx_tex_aniso {
> A6XX_TEX_ANISO_16 = 4,
> };
>
> +enum a6xx_reduction_mode {
> + A6XX_REDUCTION_MODE_AVERAGE = 0,
> + A6XX_REDUCTION_MODE_MIN = 1,
> + A6XX_REDUCTION_MODE_MAX = 2,
> +};
> +
> enum a6xx_tex_swiz {
> A6XX_TEX_X = 0,
> A6XX_TEX_Y = 1,
> @@ -1035,6 +1005,9 @@ enum a6xx_tex_type {
>
> #define REG_A6XX_CP_SQE_CNTL 0x00000808
>
> +#define REG_A6XX_CP_CP2GMU_STATUS 0x00000812
> +#define A6XX_CP_CP2GMU_STATUS_IFPC 0x00000001
> +
> #define REG_A6XX_CP_HW_FAULT 0x00000821
>
> #define REG_A6XX_CP_INTERRUPT_STATUS 0x00000823
> @@ -1050,8 +1023,44 @@ enum a6xx_tex_type {
> #define REG_A6XX_CP_APRIV_CNTL 0x00000844
>
> #define REG_A6XX_CP_ROQ_THRESHOLDS_1 0x000008c1
> +#define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__MASK 0x000000ff
> +#define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__SHIFT 0
> +static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_LO(uint32_t val)
> +{
> + return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__MASK;
> +}
> +#define A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__MASK 0x0000ff00
> +#define A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__SHIFT 8
> +static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_HI(uint32_t val)
> +{
> + return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__MASK;
> +}
> +#define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK 0x00ff0000
> +#define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT 16
> +static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val)
> +{
> + return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK;
> +}
> +#define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK 0xff000000
> +#define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT 24
> +static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val)
> +{
> + return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK;
> +}
>
> #define REG_A6XX_CP_ROQ_THRESHOLDS_2 0x000008c2
> +#define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK 0x000001ff
> +#define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT 0
> +static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val)
> +{
> + return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK;
> +}
> +#define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK 0xffff0000
> +#define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT 16
> +static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val)
> +{
> + return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK;
> +}
>
> #define REG_A6XX_CP_MEM_POOL_SIZE 0x000008c3
>
> @@ -1170,6 +1179,36 @@ static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
>
> #define REG_A6XX_CP_IB2_REM_SIZE 0x0000092d
>
> +#define REG_A6XX_CP_SDS_BASE 0x0000092e
> +
> +#define REG_A6XX_CP_SDS_BASE_HI 0x0000092f
> +
> +#define REG_A6XX_CP_SDS_REM_SIZE 0x0000092e
> +
> +#define REG_A6XX_CP_BIN_SIZE_ADDRESS 0x00000931
> +
> +#define REG_A6XX_CP_BIN_SIZE_ADDRESS_HI 0x00000932
> +
> +#define REG_A6XX_CP_BIN_DATA_ADDR 0x00000934
> +
> +#define REG_A6XX_CP_BIN_DATA_ADDR_HI 0x00000935
> +
> +#define REG_A6XX_CP_CSQ_IB1_STAT 0x00000949
> +#define A6XX_CP_CSQ_IB1_STAT_REM__MASK 0xffff0000
> +#define A6XX_CP_CSQ_IB1_STAT_REM__SHIFT 16
> +static inline uint32_t A6XX_CP_CSQ_IB1_STAT_REM(uint32_t val)
> +{
> + return ((val) << A6XX_CP_CSQ_IB1_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB1_STAT_REM__MASK;
> +}
> +
> +#define REG_A6XX_CP_CSQ_IB2_STAT 0x0000094a
> +#define A6XX_CP_CSQ_IB2_STAT_REM__MASK 0xffff0000
> +#define A6XX_CP_CSQ_IB2_STAT_REM__SHIFT 16
> +static inline uint32_t A6XX_CP_CSQ_IB2_STAT_REM(uint32_t val)
> +{
> + return ((val) << A6XX_CP_CSQ_IB2_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB2_STAT_REM__MASK;
> +}
> +
> #define REG_A6XX_CP_ALWAYS_ON_COUNTER_LO 0x00000980
>
> #define REG_A6XX_CP_ALWAYS_ON_COUNTER_HI 0x00000981
> @@ -1211,6 +1250,7 @@ static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
> #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER 0x00000001
>
> #define REG_A6XX_RBBM_STATUS3 0x00000213
> +#define A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT 0x01000000
>
> #define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS 0x00000215
>
> @@ -1428,18 +1468,6 @@ static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
>
> #define REG_A6XX_RBBM_PERFCTR_TSE_2_LO 0x0000046a
>
> -#define REG_A6XX_RBBM_PERFCTR_CCU_4_HI 0x00000465
> -
> -#define REG_A6XX_RBBM_PERFCTR_TSE_0_LO 0x00000466
> -
> -#define REG_A6XX_RBBM_PERFCTR_TSE_0_HI 0x00000467
> -
> -#define REG_A6XX_RBBM_PERFCTR_TSE_1_LO 0x00000468
> -
> -#define REG_A6XX_RBBM_PERFCTR_TSE_1_HI 0x00000469
> -
> -#define REG_A6XX_RBBM_PERFCTR_TSE_2_LO 0x0000046a
> -
> #define REG_A6XX_RBBM_PERFCTR_TSE_2_HI 0x0000046b
>
> #define REG_A6XX_RBBM_PERFCTR_TSE_3_LO 0x0000046c
> @@ -1752,6 +1780,50 @@ static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
>
> #define REG_A6XX_RBBM_ISDB_CNT 0x00000533
>
> +#define REG_A6XX_RBBM_PRIMCTR_0_LO 0x00000540
> +
> +#define REG_A6XX_RBBM_PRIMCTR_0_HI 0x00000541
> +
> +#define REG_A6XX_RBBM_PRIMCTR_1_LO 0x00000542
> +
> +#define REG_A6XX_RBBM_PRIMCTR_1_HI 0x00000543
> +
> +#define REG_A6XX_RBBM_PRIMCTR_2_LO 0x00000544
> +
> +#define REG_A6XX_RBBM_PRIMCTR_2_HI 0x00000545
> +
> +#define REG_A6XX_RBBM_PRIMCTR_3_LO 0x00000546
> +
> +#define REG_A6XX_RBBM_PRIMCTR_3_HI 0x00000547
> +
> +#define REG_A6XX_RBBM_PRIMCTR_4_LO 0x00000548
> +
> +#define REG_A6XX_RBBM_PRIMCTR_4_HI 0x00000549
> +
> +#define REG_A6XX_RBBM_PRIMCTR_5_LO 0x0000054a
> +
> +#define REG_A6XX_RBBM_PRIMCTR_5_HI 0x0000054b
> +
> +#define REG_A6XX_RBBM_PRIMCTR_6_LO 0x0000054c
> +
> +#define REG_A6XX_RBBM_PRIMCTR_6_HI 0x0000054d
> +
> +#define REG_A6XX_RBBM_PRIMCTR_7_LO 0x0000054e
> +
> +#define REG_A6XX_RBBM_PRIMCTR_7_HI 0x0000054f
> +
> +#define REG_A6XX_RBBM_PRIMCTR_8_LO 0x00000550
> +
> +#define REG_A6XX_RBBM_PRIMCTR_8_HI 0x00000551
> +
> +#define REG_A6XX_RBBM_PRIMCTR_9_LO 0x00000552
> +
> +#define REG_A6XX_RBBM_PRIMCTR_9_HI 0x00000553
> +
> +#define REG_A6XX_RBBM_PRIMCTR_10_LO 0x00000554
> +
> +#define REG_A6XX_RBBM_PRIMCTR_10_HI 0x00000555
> +
> #define REG_A6XX_RBBM_SECVID_TRUST_CNTL 0x0000f400
>
> #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800
> @@ -1768,6 +1840,9 @@ static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
>
> #define REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL 0x00000011
>
> +#define REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD 0x0000001c
> +#define A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE 0x00000001
> +
> #define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000001f
>
> #define REG_A6XX_RBBM_INT_CLEAR_CMD 0x00000037
> @@ -2670,9 +2745,11 @@ static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
> return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK;
> }
>
> -#define REG_A6XX_VSC_SIZE_ADDRESS_LO 0x00000c03
> +#define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS_LO 0x00000c03
> +
> +#define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS_HI 0x00000c04
>
> -#define REG_A6XX_VSC_SIZE_ADDRESS_HI 0x00000c04
> +#define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS 0x00000c03
>
> #define REG_A6XX_VSC_BIN_COUNT 0x00000c06
> #define A6XX_VSC_BIN_COUNT_NX__MASK 0x000007fe
> @@ -2716,53 +2793,70 @@ static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
> return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK;
> }
>
> -#define REG_A6XX_VSC_PIPE_DATA2_ADDRESS_LO 0x00000c30
> +#define REG_A6XX_VSC_PRIM_STRM_ADDRESS_LO 0x00000c30
>
> -#define REG_A6XX_VSC_PIPE_DATA2_ADDRESS_HI 0x00000c31
> +#define REG_A6XX_VSC_PRIM_STRM_ADDRESS_HI 0x00000c31
>
> -#define REG_A6XX_VSC_PIPE_DATA2_PITCH 0x00000c32
> +#define REG_A6XX_VSC_PRIM_STRM_ADDRESS 0x00000c30
>
> -#define REG_A6XX_VSC_PIPE_DATA2_ARRAY_PITCH 0x00000c33
> -#define A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__MASK 0xffffffff
> -#define A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__SHIFT 0
> -static inline uint32_t A6XX_VSC_PIPE_DATA2_ARRAY_PITCH(uint32_t val)
> -{
> - return ((val >> 4) << A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__SHIFT) & A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__MASK;
> -}
> +#define REG_A6XX_VSC_PRIM_STRM_PITCH 0x00000c32
>
> -#define REG_A6XX_VSC_PIPE_DATA_ADDRESS_LO 0x00000c34
> +#define REG_A6XX_VSC_PRIM_STRM_LIMIT 0x00000c33
>
> -#define REG_A6XX_VSC_PIPE_DATA_ADDRESS_HI 0x00000c35
> +#define REG_A6XX_VSC_DRAW_STRM_ADDRESS_LO 0x00000c34
>
> -#define REG_A6XX_VSC_PIPE_DATA_PITCH 0x00000c36
> +#define REG_A6XX_VSC_DRAW_STRM_ADDRESS_HI 0x00000c35
>
> -#define REG_A6XX_VSC_PIPE_DATA_ARRAY_PITCH 0x00000c37
> -#define A6XX_VSC_PIPE_DATA_ARRAY_PITCH__MASK 0xffffffff
> -#define A6XX_VSC_PIPE_DATA_ARRAY_PITCH__SHIFT 0
> -static inline uint32_t A6XX_VSC_PIPE_DATA_ARRAY_PITCH(uint32_t val)
> -{
> - return ((val >> 4) << A6XX_VSC_PIPE_DATA_ARRAY_PITCH__SHIFT) & A6XX_VSC_PIPE_DATA_ARRAY_PITCH__MASK;
> -}
> +#define REG_A6XX_VSC_DRAW_STRM_ADDRESS 0x00000c34
> +
> +#define REG_A6XX_VSC_DRAW_STRM_PITCH 0x00000c36
> +
> +#define REG_A6XX_VSC_DRAW_STRM_LIMIT 0x00000c37
> +
> +static inline uint32_t REG_A6XX_VSC_STATE(uint32_t i0) { return 0x00000c38 + 0x1*i0; }
> +
> +static inline uint32_t REG_A6XX_VSC_STATE_REG(uint32_t i0) { return 0x00000c38 + 0x1*i0; }
>
> -static inline uint32_t REG_A6XX_VSC_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
> +static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE(uint32_t i0) { return 0x00000c58 + 0x1*i0; }
>
> -static inline uint32_t REG_A6XX_VSC_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
> +static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE_REG(uint32_t i0) { return 0x00000c58 + 0x1*i0; }
> +
> +static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
> +
> +static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
>
> #define REG_A6XX_UCHE_UNKNOWN_0E12 0x00000e12
>
> -#define REG_A6XX_GRAS_UNKNOWN_8000 0x00008000
> +#define REG_A6XX_GRAS_CL_CNTL 0x00008000
> +#define A6XX_GRAS_CL_CNTL_CLIP_DISABLE 0x00000001
> +#define A6XX_GRAS_CL_CNTL_ZNEAR_CLIP_DISABLE 0x00000002
> +#define A6XX_GRAS_CL_CNTL_ZFAR_CLIP_DISABLE 0x00000004
> +#define A6XX_GRAS_CL_CNTL_UNK5 0x00000020
> +#define A6XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040
> +#define A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE 0x00000080
> +#define A6XX_GRAS_CL_CNTL_VP_XFORM_DISABLE 0x00000100
> +#define A6XX_GRAS_CL_CNTL_PERSP_DIVISION_DISABLE 0x00000200
>
> #define REG_A6XX_GRAS_UNKNOWN_8001 0x00008001
>
> -#define REG_A6XX_GRAS_UNKNOWN_8004 0x00008004
> +#define REG_A6XX_GRAS_UNKNOWN_8002 0x00008002
> +
> +#define REG_A6XX_GRAS_UNKNOWN_8003 0x00008003
> +
> +#define REG_A6XX_GRAS_MAX_LAYER_INDEX 0x00008004
>
> #define REG_A6XX_GRAS_CNTL 0x00008005
> -#define A6XX_GRAS_CNTL_VARYING 0x00000001
> -#define A6XX_GRAS_CNTL_UNK3 0x00000008
> -#define A6XX_GRAS_CNTL_XCOORD 0x00000040
> -#define A6XX_GRAS_CNTL_YCOORD 0x00000080
> -#define A6XX_GRAS_CNTL_ZCOORD 0x00000100
> -#define A6XX_GRAS_CNTL_WCOORD 0x00000200
> +#define A6XX_GRAS_CNTL_IJ_PERSP_PIXEL 0x00000001
> +#define A6XX_GRAS_CNTL_IJ_PERSP_CENTROID 0x00000002
> +#define A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE 0x00000004
> +#define A6XX_GRAS_CNTL_SIZE 0x00000008
> +#define A6XX_GRAS_CNTL_SIZE_PERSAMP 0x00000020
> +#define A6XX_GRAS_CNTL_COORD_MASK__MASK 0x000003c0
> +#define A6XX_GRAS_CNTL_COORD_MASK__SHIFT 6
> +static inline uint32_t A6XX_GRAS_CNTL_COORD_MASK(uint32_t val)
> +{
> + return ((val) << A6XX_GRAS_CNTL_COORD_MASK__SHIFT) & A6XX_GRAS_CNTL_COORD_MASK__MASK;
> +}
>
> #define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x00008006
> #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000003ff
> @@ -2826,6 +2920,22 @@ static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE_0(float val)
> return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
> }
>
> +#define REG_A6XX_GRAS_CL_Z_CLAMP_MIN 0x00008070
> +#define A6XX_GRAS_CL_Z_CLAMP_MIN__MASK 0xffffffff
> +#define A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT 0
> +static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MIN(float val)
> +{
> + return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MIN__MASK;
> +}
> +
> +#define REG_A6XX_GRAS_CL_Z_CLAMP_MAX 0x00008071
> +#define A6XX_GRAS_CL_Z_CLAMP_MAX__MASK 0xffffffff
> +#define A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT 0
> +static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MAX(float val)
> +{
> + return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MAX__MASK;
> +}
> +
> #define REG_A6XX_GRAS_SU_CNTL 0x00008090
> #define A6XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001
> #define A6XX_GRAS_SU_CNTL_CULL_BACK 0x00000002
> @@ -2862,7 +2972,12 @@ static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val)
> }
>
> #define REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL 0x00008094
> -#define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001
> +#define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK 0x00000003
> +#define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT 0
> +static inline uint32_t A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val)
> +{
> + return ((val) << A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK;
> +}
>
> #define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE 0x00008095
> #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
> @@ -2900,6 +3015,11 @@ static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_dep
>
> #define REG_A6XX_GRAS_UNKNOWN_809B 0x0000809b
>
> +#define REG_A6XX_GRAS_UNKNOWN_809C 0x0000809c
> +#define A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER 0x00000001
> +
> +#define REG_A6XX_GRAS_UNKNOWN_809D 0x0000809d
> +
> #define REG_A6XX_GRAS_UNKNOWN_80A0 0x000080a0
>
> #define REG_A6XX_GRAS_RAS_MSAA_CNTL 0x000080a2
> @@ -2919,11 +3039,108 @@ static inline uint32_t A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples v
> }
> #define A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
>
> -#define REG_A6XX_GRAS_UNKNOWN_80A4 0x000080a4
> +#define REG_A6XX_GRAS_SAMPLE_CONFIG 0x000080a4
> +#define A6XX_GRAS_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002
>
> -#define REG_A6XX_GRAS_UNKNOWN_80A5 0x000080a5
> +#define REG_A6XX_GRAS_SAMPLE_LOCATION_0 0x000080a5
> +#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f
> +#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0
> +static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
> +}
> +#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0
> +#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4
> +static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
> +}
> +#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00
> +#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8
> +static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
> +}
> +#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000
> +#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12
> +static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
> +}
> +#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000
> +#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16
> +static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
> +}
> +#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000
> +#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20
> +static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
> +}
> +#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000
> +#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24
> +static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
> +}
> +#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000
> +#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28
> +static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
> +}
>
> -#define REG_A6XX_GRAS_UNKNOWN_80A6 0x000080a6
> +#define REG_A6XX_GRAS_SAMPLE_LOCATION_1 0x000080a6
> +#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f
> +#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0
> +static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
> +}
> +#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0
> +#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4
> +static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
> +}
> +#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00
> +#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8
> +static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
> +}
> +#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000
> +#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12
> +static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
> +}
> +#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000
> +#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16
> +static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
> +}
> +#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000
> +#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20
> +static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
> +}
> +#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000
> +#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24
> +static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
> +}
> +#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000
> +#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28
> +static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
> +}
>
> #define REG_A6XX_GRAS_UNKNOWN_80AF 0x000080af
>
> @@ -3021,15 +3238,15 @@ static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
> #define A6XX_GRAS_LRZ_CNTL_ENABLE 0x00000001
> #define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002
> #define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004
> -#define A6XX_GRAS_LRZ_CNTL_UNK3 0x00000008
> -#define A6XX_GRAS_LRZ_CNTL_UNK4 0x00000010
> +#define A6XX_GRAS_LRZ_CNTL_FC_ENABLE 0x00000008
> +#define A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE 0x00000010
>
> #define REG_A6XX_GRAS_UNKNOWN_8101 0x00008101
>
> #define REG_A6XX_GRAS_2D_BLIT_INFO 0x00008102
> #define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK 0x000000ff
> #define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT 0
> -static inline uint32_t A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
> +static inline uint32_t A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT(enum a6xx_format val)
> {
> return ((val) << A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK;
> }
> @@ -3038,6 +3255,8 @@ static inline uint32_t A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT(enum a6xx_color_fmt v
>
> #define REG_A6XX_GRAS_LRZ_BUFFER_BASE_HI 0x00008104
>
> +#define REG_A6XX_GRAS_LRZ_BUFFER_BASE 0x00008103
> +
> #define REG_A6XX_GRAS_LRZ_BUFFER_PITCH 0x00008105
> #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK 0x000007ff
> #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT 0
> @@ -3056,47 +3275,76 @@ static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
>
> #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x00008107
>
> -#define REG_A6XX_GRAS_UNKNOWN_8109 0x00008109
> +#define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE 0x00008106
> +
> +#define REG_A6XX_GRAS_SAMPLE_CNTL 0x00008109
> +#define A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001
>
> #define REG_A6XX_GRAS_UNKNOWN_8110 0x00008110
>
> #define REG_A6XX_GRAS_2D_BLIT_CNTL 0x00008400
> +#define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK 0x00000007
> +#define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT 0
> +static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val)
> +{
> + return ((val) << A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK;
> +}
> +#define A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR 0x00000080
> #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00
> #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8
> -static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_color_fmt val)
> +static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val)
> {
> return ((val) << A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK;
> }
> #define A6XX_GRAS_2D_BLIT_CNTL_SCISSOR 0x00010000
> +#define A6XX_GRAS_2D_BLIT_CNTL_UNK__MASK 0x00060000
> +#define A6XX_GRAS_2D_BLIT_CNTL_UNK__SHIFT 17
> +static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK(uint32_t val)
> +{
> + return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK__MASK;
> +}
> +#define A6XX_GRAS_2D_BLIT_CNTL_D24S8 0x00080000
> +#define A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK 0x00f00000
> +#define A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT 20
> +static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_MASK(uint32_t val)
> +{
> + return ((val) << A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK;
> +}
> +#define A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK 0x1f000000
> +#define A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT 24
> +static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val)
> +{
> + return ((val) << A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK;
> +}
>
> #define REG_A6XX_GRAS_2D_SRC_TL_X 0x00008401
> -#define A6XX_GRAS_2D_SRC_TL_X_X__MASK 0x00ffff00
> +#define A6XX_GRAS_2D_SRC_TL_X_X__MASK 0xffffff00
> #define A6XX_GRAS_2D_SRC_TL_X_X__SHIFT 8
> -static inline uint32_t A6XX_GRAS_2D_SRC_TL_X_X(uint32_t val)
> +static inline uint32_t A6XX_GRAS_2D_SRC_TL_X_X(int32_t val)
> {
> return ((val) << A6XX_GRAS_2D_SRC_TL_X_X__SHIFT) & A6XX_GRAS_2D_SRC_TL_X_X__MASK;
> }
>
> #define REG_A6XX_GRAS_2D_SRC_BR_X 0x00008402
> -#define A6XX_GRAS_2D_SRC_BR_X_X__MASK 0x00ffff00
> +#define A6XX_GRAS_2D_SRC_BR_X_X__MASK 0xffffff00
> #define A6XX_GRAS_2D_SRC_BR_X_X__SHIFT 8
> -static inline uint32_t A6XX_GRAS_2D_SRC_BR_X_X(uint32_t val)
> +static inline uint32_t A6XX_GRAS_2D_SRC_BR_X_X(int32_t val)
> {
> return ((val) << A6XX_GRAS_2D_SRC_BR_X_X__SHIFT) & A6XX_GRAS_2D_SRC_BR_X_X__MASK;
> }
>
> #define REG_A6XX_GRAS_2D_SRC_TL_Y 0x00008403
> -#define A6XX_GRAS_2D_SRC_TL_Y_Y__MASK 0x00ffff00
> +#define A6XX_GRAS_2D_SRC_TL_Y_Y__MASK 0xffffff00
> #define A6XX_GRAS_2D_SRC_TL_Y_Y__SHIFT 8
> -static inline uint32_t A6XX_GRAS_2D_SRC_TL_Y_Y(uint32_t val)
> +static inline uint32_t A6XX_GRAS_2D_SRC_TL_Y_Y(int32_t val)
> {
> return ((val) << A6XX_GRAS_2D_SRC_TL_Y_Y__SHIFT) & A6XX_GRAS_2D_SRC_TL_Y_Y__MASK;
> }
>
> #define REG_A6XX_GRAS_2D_SRC_BR_Y 0x00008404
> -#define A6XX_GRAS_2D_SRC_BR_Y_Y__MASK 0x00ffff00
> +#define A6XX_GRAS_2D_SRC_BR_Y_Y__MASK 0xffffff00
> #define A6XX_GRAS_2D_SRC_BR_Y_Y__SHIFT 8
> -static inline uint32_t A6XX_GRAS_2D_SRC_BR_Y_Y(uint32_t val)
> +static inline uint32_t A6XX_GRAS_2D_SRC_BR_Y_Y(int32_t val)
> {
> return ((val) << A6XX_GRAS_2D_SRC_BR_Y_Y__SHIFT) & A6XX_GRAS_2D_SRC_BR_Y_Y__MASK;
> }
> @@ -3207,28 +3455,135 @@ static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val
> }
> #define A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
>
> -#define REG_A6XX_RB_UNKNOWN_8804 0x00008804
> +#define REG_A6XX_RB_SAMPLE_CONFIG 0x00008804
> +#define A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002
>
> -#define REG_A6XX_RB_UNKNOWN_8805 0x00008805
> +#define REG_A6XX_RB_SAMPLE_LOCATION_0 0x00008805
> +#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f
> +#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0
> +static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
> +}
> +#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0
> +#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4
> +static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
> +}
> +#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00
> +#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8
> +static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
> +}
> +#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000
> +#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12
> +static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
> +}
> +#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000
> +#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16
> +static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
> +}
> +#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000
> +#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20
> +static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
> +}
> +#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000
> +#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24
> +static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
> +}
> +#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000
> +#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28
> +static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
> +}
>
> -#define REG_A6XX_RB_UNKNOWN_8806 0x00008806
> +#define REG_A6XX_RB_SAMPLE_LOCATION_1 0x00008806
> +#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f
> +#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0
> +static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
> +}
> +#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0
> +#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4
> +static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
> +}
> +#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00
> +#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8
> +static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
> +}
> +#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000
> +#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12
> +static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
> +}
> +#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000
> +#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16
> +static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
> +}
> +#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000
> +#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20
> +static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
> +}
> +#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000
> +#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24
> +static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
> +}
> +#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000
> +#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28
> +static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
> +}
>
> #define REG_A6XX_RB_RENDER_CONTROL0 0x00008809
> -#define A6XX_RB_RENDER_CONTROL0_VARYING 0x00000001
> -#define A6XX_RB_RENDER_CONTROL0_UNK3 0x00000008
> -#define A6XX_RB_RENDER_CONTROL0_XCOORD 0x00000040
> -#define A6XX_RB_RENDER_CONTROL0_YCOORD 0x00000080
> -#define A6XX_RB_RENDER_CONTROL0_ZCOORD 0x00000100
> -#define A6XX_RB_RENDER_CONTROL0_WCOORD 0x00000200
> +#define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL 0x00000001
> +#define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID 0x00000002
> +#define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE 0x00000004
> +#define A6XX_RB_RENDER_CONTROL0_SIZE 0x00000008
> +#define A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP 0x00000020
> +#define A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK 0x000003c0
> +#define A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT 6
> +static inline uint32_t A6XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val)
> +{
> + return ((val) << A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT) & A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK;
> +}
> #define A6XX_RB_RENDER_CONTROL0_UNK10 0x00000400
>
> #define REG_A6XX_RB_RENDER_CONTROL1 0x0000880a
> #define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001
> -#define A6XX_RB_RENDER_CONTROL1_FACENESS 0x00000002
> +#define A6XX_RB_RENDER_CONTROL1_FACENESS 0x00000004
> #define A6XX_RB_RENDER_CONTROL1_SAMPLEID 0x00000008
> +#define A6XX_RB_RENDER_CONTROL1_UNK4 0x00000010
> +#define A6XX_RB_RENDER_CONTROL1_UNK5 0x00000020
> +#define A6XX_RB_RENDER_CONTROL1_SIZE 0x00000040
>
> #define REG_A6XX_RB_FS_OUTPUT_CNTL0 0x0000880b
> +#define A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE 0x00000001
> #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z 0x00000002
> +#define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK 0x00000004
>
> #define REG_A6XX_RB_FS_OUTPUT_CNTL1 0x0000880c
> #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f
> @@ -3348,7 +3703,8 @@ static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dithe
> #define A6XX_RB_SRGB_CNTL_SRGB_MRT6 0x00000040
> #define A6XX_RB_SRGB_CNTL_SRGB_MRT7 0x00000080
>
> -#define REG_A6XX_RB_UNKNOWN_8810 0x00008810
> +#define REG_A6XX_RB_SAMPLE_CNTL 0x00008810
> +#define A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001
>
> #define REG_A6XX_RB_UNKNOWN_8811 0x00008811
>
> @@ -3426,7 +3782,7 @@ static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_r
> static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; }
> #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff
> #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
> -static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
> +static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val)
> {
> return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
> }
> @@ -3463,6 +3819,8 @@ static inline uint32_t REG_A6XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x00008825
>
> static inline uint32_t REG_A6XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x00008826 + 0x8*i0; }
>
> +static inline uint32_t REG_A6XX_RB_MRT_BASE(uint32_t i0) { return 0x00008825 + 0x8*i0; }
> +
> static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; }
>
> #define REG_A6XX_RB_BLEND_RED_F32 0x00008860
> @@ -3520,7 +3878,9 @@ static inline uint32_t A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
> return ((val) << A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK;
> }
> #define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100
> +#define A6XX_RB_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200
> #define A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
> +#define A6XX_RB_BLEND_CNTL_ALPHA_TO_ONE 0x00000800
> #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000
> #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16
> static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
> @@ -3529,7 +3889,12 @@ static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
> }
>
> #define REG_A6XX_RB_DEPTH_PLANE_CNTL 0x00008870
> -#define A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001
> +#define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK 0x00000003
> +#define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT 0
> +static inline uint32_t A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val)
> +{
> + return ((val) << A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK;
> +}
>
> #define REG_A6XX_RB_DEPTH_CNTL 0x00008871
> #define A6XX_RB_DEPTH_CNTL_Z_ENABLE 0x00000001
> @@ -3540,7 +3905,9 @@ static inline uint32_t A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val)
> {
> return ((val) << A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK;
> }
> +#define A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE 0x00000020
> #define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000040
> +#define A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE 0x00000080
>
> #define REG_A6XX_RB_DEPTH_BUFFER_INFO 0x00008872
> #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
> @@ -3570,11 +3937,25 @@ static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)
>
> #define REG_A6XX_RB_DEPTH_BUFFER_BASE_HI 0x00008876
>
> +#define REG_A6XX_RB_DEPTH_BUFFER_BASE 0x00008875
> +
> #define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM 0x00008877
>
> -#define REG_A6XX_RB_UNKNOWN_8878 0x00008878
> +#define REG_A6XX_RB_Z_BOUNDS_MIN 0x00008878
> +#define A6XX_RB_Z_BOUNDS_MIN__MASK 0xffffffff
> +#define A6XX_RB_Z_BOUNDS_MIN__SHIFT 0
> +static inline uint32_t A6XX_RB_Z_BOUNDS_MIN(float val)
> +{
> + return ((fui(val)) << A6XX_RB_Z_BOUNDS_MIN__SHIFT) & A6XX_RB_Z_BOUNDS_MIN__MASK;
> +}
>
> -#define REG_A6XX_RB_UNKNOWN_8879 0x00008879
> +#define REG_A6XX_RB_Z_BOUNDS_MAX 0x00008879
> +#define A6XX_RB_Z_BOUNDS_MAX__MASK 0xffffffff
> +#define A6XX_RB_Z_BOUNDS_MAX__SHIFT 0
> +static inline uint32_t A6XX_RB_Z_BOUNDS_MAX(float val)
> +{
> + return ((fui(val)) << A6XX_RB_Z_BOUNDS_MAX__SHIFT) & A6XX_RB_Z_BOUNDS_MAX__MASK;
> +}
>
> #define REG_A6XX_RB_STENCIL_CONTROL 0x00008880
> #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
> @@ -3652,6 +4033,8 @@ static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val)
>
> #define REG_A6XX_RB_STENCIL_BUFFER_BASE_HI 0x00008885
>
> +#define REG_A6XX_RB_STENCIL_BUFFER_BASE 0x00008884
> +
> #define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM 0x00008886
>
> #define REG_A6XX_RB_STENCILREF 0x00008887
> @@ -3717,6 +4100,22 @@ static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val)
> #define REG_A6XX_RB_LRZ_CNTL 0x00008898
> #define A6XX_RB_LRZ_CNTL_ENABLE 0x00000001
>
> +#define REG_A6XX_RB_Z_CLAMP_MIN 0x000088c0
> +#define A6XX_RB_Z_CLAMP_MIN__MASK 0xffffffff
> +#define A6XX_RB_Z_CLAMP_MIN__SHIFT 0
> +static inline uint32_t A6XX_RB_Z_CLAMP_MIN(float val)
> +{
> + return ((fui(val)) << A6XX_RB_Z_CLAMP_MIN__SHIFT) & A6XX_RB_Z_CLAMP_MIN__MASK;
> +}
> +
> +#define REG_A6XX_RB_Z_CLAMP_MAX 0x000088c1
> +#define A6XX_RB_Z_CLAMP_MAX__MASK 0xffffffff
> +#define A6XX_RB_Z_CLAMP_MAX__SHIFT 0
> +static inline uint32_t A6XX_RB_Z_CLAMP_MAX(float val)
> +{
> + return ((fui(val)) << A6XX_RB_Z_CLAMP_MAX__SHIFT) & A6XX_RB_Z_CLAMP_MAX__MASK;
> +}
> +
> #define REG_A6XX_RB_UNKNOWN_88D0 0x000088d0
>
> #define REG_A6XX_RB_BLIT_SCISSOR_TL 0x000088d1
> @@ -3775,7 +4174,7 @@ static inline uint32_t A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val)
> }
> #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK 0x00007f80
> #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT 7
> -static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
> +static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_format val)
> {
> return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK;
> }
> @@ -3786,6 +4185,8 @@ static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val
> return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK;
> }
>
> +#define REG_A6XX_RB_BLIT_DST 0x000088d8
> +
> #define REG_A6XX_RB_BLIT_DST_LO 0x000088d8
>
> #define REG_A6XX_RB_BLIT_DST_HI 0x000088d9
> @@ -3806,10 +4207,26 @@ static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)
> return ((val >> 6) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK;
> }
>
> +#define REG_A6XX_RB_BLIT_FLAG_DST 0x000088dc
> +
> #define REG_A6XX_RB_BLIT_FLAG_DST_LO 0x000088dc
>
> #define REG_A6XX_RB_BLIT_FLAG_DST_HI 0x000088dd
>
> +#define REG_A6XX_RB_BLIT_FLAG_DST_PITCH 0x000088de
> +#define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK 0x000007ff
> +#define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT 0
> +static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(uint32_t val)
> +{
> + return ((val >> 6) << A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK;
> +}
> +#define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK 0x003ff800
> +#define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT 11
> +static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val)
> +{
> + return ((val >> 7) << A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK;
> +}
> +
> #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0 0x000088df
>
> #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1 0x000088e0
> @@ -3836,7 +4253,21 @@ static inline uint32_t A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val)
>
> #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x00008901
>
> +#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE 0x00008900
> +
> #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x00008902
> +#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff
> +#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT 0
> +static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
> +{
> + return ((val >> 6) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK;
> +}
> +#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x01fff800
> +#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
> +static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
> +{
> + return ((val >> 7) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
> +}
>
> static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; }
>
> @@ -3844,18 +4275,20 @@ static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return
>
> static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x00008904 + 0x3*i0; }
>
> +static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) { return 0x00008903 + 0x3*i0; }
> +
> static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0; }
> #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff
> #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT 0
> static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
> {
> - return ((val >> 5) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK;
> + return ((val >> 6) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK;
> }
> -#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x003ff800
> +#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x01fff800
> #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
> static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
> {
> - return ((val >> 5) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
> + return ((val >> 7) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
> }
>
> #define REG_A6XX_RB_SAMPLE_COUNT_ADDR_LO 0x00008927
> @@ -3863,20 +4296,46 @@ static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
> #define REG_A6XX_RB_SAMPLE_COUNT_ADDR_HI 0x00008928
>
> #define REG_A6XX_RB_2D_BLIT_CNTL 0x00008c00
> +#define A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK 0x00000007
> +#define A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT 0
> +static inline uint32_t A6XX_RB_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val)
> +{
> + return ((val) << A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK;
> +}
> +#define A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR 0x00000080
> #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00
> #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8
> -static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_color_fmt val)
> +static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val)
> {
> return ((val) << A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK;
> }
> #define A6XX_RB_2D_BLIT_CNTL_SCISSOR 0x00010000
> +#define A6XX_RB_2D_BLIT_CNTL_UNK__MASK 0x00060000
> +#define A6XX_RB_2D_BLIT_CNTL_UNK__SHIFT 17
> +static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK(uint32_t val)
> +{
> + return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK__MASK;
> +}
> +#define A6XX_RB_2D_BLIT_CNTL_D24S8 0x00080000
> +#define A6XX_RB_2D_BLIT_CNTL_MASK__MASK 0x00f00000
> +#define A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT 20
> +static inline uint32_t A6XX_RB_2D_BLIT_CNTL_MASK(uint32_t val)
> +{
> + return ((val) << A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_RB_2D_BLIT_CNTL_MASK__MASK;
> +}
> +#define A6XX_RB_2D_BLIT_CNTL_IFMT__MASK 0x1f000000
> +#define A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT 24
> +static inline uint32_t A6XX_RB_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val)
> +{
> + return ((val) << A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_IFMT__MASK;
> +}
>
> #define REG_A6XX_RB_UNKNOWN_8C01 0x00008c01
>
> #define REG_A6XX_RB_2D_DST_INFO 0x00008c17
> #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
> #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0
> -static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
> +static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_format val)
> {
> return ((val) << A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK;
> }
> @@ -3893,11 +4352,24 @@ static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
> return ((val) << A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK;
> }
> #define A6XX_RB_2D_DST_INFO_FLAGS 0x00001000
> +#define A6XX_RB_2D_DST_INFO_SRGB 0x00002000
> +#define A6XX_RB_2D_DST_INFO_SAMPLES__MASK 0x0000c000
> +#define A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT 14
> +static inline uint32_t A6XX_RB_2D_DST_INFO_SAMPLES(enum a3xx_msaa_samples val)
> +{
> + return ((val) << A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_2D_DST_INFO_SAMPLES__MASK;
> +}
> +#define A6XX_RB_2D_DST_INFO_FILTER 0x00010000
> +#define A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE 0x00040000
> +#define A6XX_RB_2D_DST_INFO_UNK20 0x00100000
> +#define A6XX_RB_2D_DST_INFO_UNK22 0x00400000
>
> #define REG_A6XX_RB_2D_DST_LO 0x00008c18
>
> #define REG_A6XX_RB_2D_DST_HI 0x00008c19
>
> +#define REG_A6XX_RB_2D_DST 0x00008c18
> +
> #define REG_A6XX_RB_2D_DST_SIZE 0x00008c1a
> #define A6XX_RB_2D_DST_SIZE_PITCH__MASK 0x0000ffff
> #define A6XX_RB_2D_DST_SIZE_PITCH__SHIFT 0
> @@ -3910,6 +4382,22 @@ static inline uint32_t A6XX_RB_2D_DST_SIZE_PITCH(uint32_t val)
>
> #define REG_A6XX_RB_2D_DST_FLAGS_HI 0x00008c21
>
> +#define REG_A6XX_RB_2D_DST_FLAGS 0x00008c20
> +
> +#define REG_A6XX_RB_2D_DST_FLAGS_PITCH 0x00008c22
> +#define A6XX_RB_2D_DST_FLAGS_PITCH_PITCH__MASK 0x000007ff
> +#define A6XX_RB_2D_DST_FLAGS_PITCH_PITCH__SHIFT 0
> +static inline uint32_t A6XX_RB_2D_DST_FLAGS_PITCH_PITCH(uint32_t val)
> +{
> + return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PITCH_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH_PITCH__MASK;
> +}
> +#define A6XX_RB_2D_DST_FLAGS_PITCH_ARRAY_PITCH__MASK 0x003ff800
> +#define A6XX_RB_2D_DST_FLAGS_PITCH_ARRAY_PITCH__SHIFT 11
> +static inline uint32_t A6XX_RB_2D_DST_FLAGS_PITCH_ARRAY_PITCH(uint32_t val)
> +{
> + return ((val >> 7) << A6XX_RB_2D_DST_FLAGS_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH_ARRAY_PITCH__MASK;
> +}
> +
> #define REG_A6XX_RB_2D_SRC_SOLID_C0 0x00008c2c
>
> #define REG_A6XX_RB_2D_SRC_SOLID_C1 0x00008c2d
> @@ -3923,14 +4411,44 @@ static inline uint32_t A6XX_RB_2D_DST_SIZE_PITCH(uint32_t val)
> #define REG_A6XX_RB_UNKNOWN_8E04 0x00008e04
>
> #define REG_A6XX_RB_CCU_CNTL 0x00008e07
> +#define A6XX_RB_CCU_CNTL_OFFSET__MASK 0xff800000
> +#define A6XX_RB_CCU_CNTL_OFFSET__SHIFT 23
> +static inline uint32_t A6XX_RB_CCU_CNTL_OFFSET(uint32_t val)
> +{
> + return ((val >> 12) << A6XX_RB_CCU_CNTL_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_OFFSET__MASK;
> +}
> +#define A6XX_RB_CCU_CNTL_GMEM 0x00400000
> +#define A6XX_RB_CCU_CNTL_UNK2 0x00000004
> +
> +#define REG_A6XX_VPC_UNKNOWN_9100 0x00009100
>
> #define REG_A6XX_VPC_UNKNOWN_9101 0x00009101
>
> +#define REG_A6XX_VPC_UNKNOWN_9102 0x00009102
> +
> +#define REG_A6XX_VPC_UNKNOWN_9103 0x00009103
> +
> #define REG_A6XX_VPC_GS_SIV_CNTL 0x00009104
>
> +#define REG_A6XX_VPC_UNKNOWN_9105 0x00009105
> +#define A6XX_VPC_UNKNOWN_9105_LAYERLOC__MASK 0x000000ff
> +#define A6XX_VPC_UNKNOWN_9105_LAYERLOC__SHIFT 0
> +static inline uint32_t A6XX_VPC_UNKNOWN_9105_LAYERLOC(uint32_t val)
> +{
> + return ((val) << A6XX_VPC_UNKNOWN_9105_LAYERLOC__SHIFT) & A6XX_VPC_UNKNOWN_9105_LAYERLOC__MASK;
> +}
> +
> +#define REG_A6XX_VPC_UNKNOWN_9106 0x00009106
> +
> #define REG_A6XX_VPC_UNKNOWN_9107 0x00009107
>
> -#define REG_A6XX_VPC_UNKNOWN_9108 0x00009108
> +#define REG_A6XX_VPC_POLYGON_MODE 0x00009108
> +#define A6XX_VPC_POLYGON_MODE_MODE__MASK 0x00000003
> +#define A6XX_VPC_POLYGON_MODE_MODE__SHIFT 0
> +static inline uint32_t A6XX_VPC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)
> +{
> + return ((val) << A6XX_VPC_POLYGON_MODE_MODE__SHIFT) & A6XX_VPC_POLYGON_MODE_MODE__MASK;
> +}
>
> static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; }
>
> @@ -3979,8 +4497,14 @@ static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val)
> }
> #define A6XX_VPC_SO_PROG_B_EN 0x00800000
>
> +#define REG_A6XX_VPC_SO_STREAM_COUNTS_LO 0x00009218
> +
> +#define REG_A6XX_VPC_SO_STREAM_COUNTS_HI 0x00009219
> +
> static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; }
>
> +static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE(uint32_t i0) { return 0x0000921a + 0x7*i0; }
> +
> static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000921a + 0x7*i0; }
>
> static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000921b + 0x7*i0; }
> @@ -3991,11 +4515,19 @@ static inline uint32_t REG_A6XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000921d +
>
> static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; }
>
> +static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE(uint32_t i0) { return 0x0000921f + 0x7*i0; }
> +
> static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000921f + 0x7*i0; }
>
> static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x00009220 + 0x7*i0; }
>
> #define REG_A6XX_VPC_UNKNOWN_9236 0x00009236
> +#define A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT__MASK 0x00000001
> +#define A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT__SHIFT 0
> +static inline uint32_t A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT(uint32_t val)
> +{
> + return ((val) << A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT__SHIFT) & A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT__MASK;
> +}
>
> #define REG_A6XX_VPC_UNKNOWN_9300 0x00009300
>
> @@ -4006,11 +4538,11 @@ static inline uint32_t A6XX_VPC_PACK_STRIDE_IN_VPC(uint32_t val)
> {
> return ((val) << A6XX_VPC_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_PACK_STRIDE_IN_VPC__MASK;
> }
> -#define A6XX_VPC_PACK_NUMNONPOSVAR__MASK 0x0000ff00
> -#define A6XX_VPC_PACK_NUMNONPOSVAR__SHIFT 8
> -static inline uint32_t A6XX_VPC_PACK_NUMNONPOSVAR(uint32_t val)
> +#define A6XX_VPC_PACK_POSITIONLOC__MASK 0x0000ff00
> +#define A6XX_VPC_PACK_POSITIONLOC__SHIFT 8
> +static inline uint32_t A6XX_VPC_PACK_POSITIONLOC(uint32_t val)
> {
> - return ((val) << A6XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A6XX_VPC_PACK_NUMNONPOSVAR__MASK;
> + return ((val) << A6XX_VPC_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_PACK_POSITIONLOC__MASK;
> }
> #define A6XX_VPC_PACK_PSIZELOC__MASK 0x00ff0000
> #define A6XX_VPC_PACK_PSIZELOC__SHIFT 16
> @@ -4019,6 +4551,46 @@ static inline uint32_t A6XX_VPC_PACK_PSIZELOC(uint32_t val)
> return ((val) << A6XX_VPC_PACK_PSIZELOC__SHIFT) & A6XX_VPC_PACK_PSIZELOC__MASK;
> }
>
> +#define REG_A6XX_VPC_PACK_GS 0x00009302
> +#define A6XX_VPC_PACK_GS_STRIDE_IN_VPC__MASK 0x000000ff
> +#define A6XX_VPC_PACK_GS_STRIDE_IN_VPC__SHIFT 0
> +static inline uint32_t A6XX_VPC_PACK_GS_STRIDE_IN_VPC(uint32_t val)
> +{
> + return ((val) << A6XX_VPC_PACK_GS_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_PACK_GS_STRIDE_IN_VPC__MASK;
> +}
> +#define A6XX_VPC_PACK_GS_POSITIONLOC__MASK 0x0000ff00
> +#define A6XX_VPC_PACK_GS_POSITIONLOC__SHIFT 8
> +static inline uint32_t A6XX_VPC_PACK_GS_POSITIONLOC(uint32_t val)
> +{
> + return ((val) << A6XX_VPC_PACK_GS_POSITIONLOC__SHIFT) & A6XX_VPC_PACK_GS_POSITIONLOC__MASK;
> +}
> +#define A6XX_VPC_PACK_GS_PSIZELOC__MASK 0x00ff0000
> +#define A6XX_VPC_PACK_GS_PSIZELOC__SHIFT 16
> +static inline uint32_t A6XX_VPC_PACK_GS_PSIZELOC(uint32_t val)
> +{
> + return ((val) << A6XX_VPC_PACK_GS_PSIZELOC__SHIFT) & A6XX_VPC_PACK_GS_PSIZELOC__MASK;
> +}
> +
> +#define REG_A6XX_VPC_PACK_3 0x00009303
> +#define A6XX_VPC_PACK_3_STRIDE_IN_VPC__MASK 0x000000ff
> +#define A6XX_VPC_PACK_3_STRIDE_IN_VPC__SHIFT 0
> +static inline uint32_t A6XX_VPC_PACK_3_STRIDE_IN_VPC(uint32_t val)
> +{
> + return ((val) << A6XX_VPC_PACK_3_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_PACK_3_STRIDE_IN_VPC__MASK;
> +}
> +#define A6XX_VPC_PACK_3_POSITIONLOC__MASK 0x0000ff00
> +#define A6XX_VPC_PACK_3_POSITIONLOC__SHIFT 8
> +static inline uint32_t A6XX_VPC_PACK_3_POSITIONLOC(uint32_t val)
> +{
> + return ((val) << A6XX_VPC_PACK_3_POSITIONLOC__SHIFT) & A6XX_VPC_PACK_3_POSITIONLOC__MASK;
> +}
> +#define A6XX_VPC_PACK_3_PSIZELOC__MASK 0x00ff0000
> +#define A6XX_VPC_PACK_3_PSIZELOC__SHIFT 16
> +static inline uint32_t A6XX_VPC_PACK_3_PSIZELOC(uint32_t val)
> +{
> + return ((val) << A6XX_VPC_PACK_3_PSIZELOC__SHIFT) & A6XX_VPC_PACK_3_PSIZELOC__MASK;
> +}
> +
> #define REG_A6XX_VPC_CNTL_0 0x00009304
> #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK 0x000000ff
> #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT 0
> @@ -4026,7 +4598,19 @@ static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val)
> {
> return ((val) << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK;
> }
> +#define A6XX_VPC_CNTL_0_PRIMIDLOC__MASK 0x0000ff00
> +#define A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT 8
> +static inline uint32_t A6XX_VPC_CNTL_0_PRIMIDLOC(uint32_t val)
> +{
> + return ((val) << A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT) & A6XX_VPC_CNTL_0_PRIMIDLOC__MASK;
> +}
> #define A6XX_VPC_CNTL_0_VARYING 0x00010000
> +#define A6XX_VPC_CNTL_0_UNKLOC__MASK 0xff000000
> +#define A6XX_VPC_CNTL_0_UNKLOC__SHIFT 24
> +static inline uint32_t A6XX_VPC_CNTL_0_UNKLOC(uint32_t val)
> +{
> + return ((val) << A6XX_VPC_CNTL_0_UNKLOC__SHIFT) & A6XX_VPC_CNTL_0_UNKLOC__MASK;
> +}
>
> #define REG_A6XX_VPC_SO_BUF_CNTL 0x00009305
> #define A6XX_VPC_SO_BUF_CNTL_BUF0 0x00000001
> @@ -4042,28 +4626,82 @@ static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val)
>
> #define REG_A6XX_VPC_UNKNOWN_9602 0x00009602
>
> +#define REG_A6XX_PC_TESS_NUM_VERTEX 0x00009800
> +
> #define REG_A6XX_PC_UNKNOWN_9801 0x00009801
>
> +#define REG_A6XX_PC_TESS_CNTL 0x00009802
> +#define A6XX_PC_TESS_CNTL_SPACING__MASK 0x00000003
> +#define A6XX_PC_TESS_CNTL_SPACING__SHIFT 0
> +static inline uint32_t A6XX_PC_TESS_CNTL_SPACING(enum a6xx_tess_spacing val)
> +{
> + return ((val) << A6XX_PC_TESS_CNTL_SPACING__SHIFT) & A6XX_PC_TESS_CNTL_SPACING__MASK;
> +}
> +#define A6XX_PC_TESS_CNTL_OUTPUT__MASK 0x0000000c
> +#define A6XX_PC_TESS_CNTL_OUTPUT__SHIFT 2
> +static inline uint32_t A6XX_PC_TESS_CNTL_OUTPUT(enum a6xx_tess_output val)
> +{
> + return ((val) << A6XX_PC_TESS_CNTL_OUTPUT__SHIFT) & A6XX_PC_TESS_CNTL_OUTPUT__MASK;
> +}
> +
> #define REG_A6XX_PC_RESTART_INDEX 0x00009803
>
> #define REG_A6XX_PC_MODE_CNTL 0x00009804
>
> #define REG_A6XX_PC_UNKNOWN_9805 0x00009805
>
> -#define REG_A6XX_PC_UNKNOWN_9806 0x00009806
> +#define REG_A6XX_PC_PRIMID_CNTL 0x00009806
> +#define A6XX_PC_PRIMID_CNTL_PRIMID_PASSTHRU 0x00000001
> +
> +#define REG_A6XX_PC_DRAW_CMD 0x00009840
> +#define A6XX_PC_DRAW_CMD_STATE_ID__MASK 0x000000ff
> +#define A6XX_PC_DRAW_CMD_STATE_ID__SHIFT 0
> +static inline uint32_t A6XX_PC_DRAW_CMD_STATE_ID(uint32_t val)
> +{
> + return ((val) << A6XX_PC_DRAW_CMD_STATE_ID__SHIFT) & A6XX_PC_DRAW_CMD_STATE_ID__MASK;
> +}
> +
> +#define REG_A6XX_PC_DISPATCH_CMD 0x00009841
> +#define A6XX_PC_DISPATCH_CMD_STATE_ID__MASK 0x000000ff
> +#define A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT 0
> +static inline uint32_t A6XX_PC_DISPATCH_CMD_STATE_ID(uint32_t val)
> +{
> + return ((val) << A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_PC_DISPATCH_CMD_STATE_ID__MASK;
> +}
> +
> +#define REG_A6XX_PC_EVENT_CMD 0x00009842
> +#define A6XX_PC_EVENT_CMD_STATE_ID__MASK 0x00ff0000
> +#define A6XX_PC_EVENT_CMD_STATE_ID__SHIFT 16
> +static inline uint32_t A6XX_PC_EVENT_CMD_STATE_ID(uint32_t val)
> +{
> + return ((val) << A6XX_PC_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_EVENT_CMD_STATE_ID__MASK;
> +}
> +#define A6XX_PC_EVENT_CMD_EVENT__MASK 0x0000007f
> +#define A6XX_PC_EVENT_CMD_EVENT__SHIFT 0
> +static inline uint32_t A6XX_PC_EVENT_CMD_EVENT(enum vgt_event_type val)
> +{
> + return ((val) << A6XX_PC_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_EVENT_CMD_EVENT__MASK;
> +}
>
> #define REG_A6XX_PC_UNKNOWN_9980 0x00009980
>
> -#define REG_A6XX_PC_UNKNOWN_9981 0x00009981
> +#define REG_A6XX_PC_POLYGON_MODE 0x00009981
> +#define A6XX_PC_POLYGON_MODE_MODE__MASK 0x00000003
> +#define A6XX_PC_POLYGON_MODE_MODE__SHIFT 0
> +static inline uint32_t A6XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)
> +{
> + return ((val) << A6XX_PC_POLYGON_MODE_MODE__SHIFT) & A6XX_PC_POLYGON_MODE_MODE__MASK;
> +}
>
> #define REG_A6XX_PC_UNKNOWN_9990 0x00009990
>
> #define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00
> #define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001
> #define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002
> +#define A6XX_PC_PRIMITIVE_CNTL_0_TESS_UPPER_LEFT_DOMAIN_ORIGIN 0x00000004
>
> #define REG_A6XX_PC_PRIMITIVE_CNTL_1 0x00009b01
> -#define A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__MASK 0x0000007f
> +#define A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__MASK 0x000000ff
> #define A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__SHIFT 0
> static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(uint32_t val)
> {
> @@ -4071,7 +4709,62 @@ static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(uint32_t val)
> }
> #define A6XX_PC_PRIMITIVE_CNTL_1_PSIZE 0x00000100
>
> -#define REG_A6XX_PC_UNKNOWN_9B06 0x00009b06
> +#define REG_A6XX_PC_PRIMITIVE_CNTL_2 0x00009b02
> +#define A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC__MASK 0x000000ff
> +#define A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC__SHIFT 0
> +static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(uint32_t val)
> +{
> + return ((val) << A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC__MASK;
> +}
> +#define A6XX_PC_PRIMITIVE_CNTL_2_PSIZE 0x00000100
> +#define A6XX_PC_PRIMITIVE_CNTL_2_LAYER 0x00000200
> +#define A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID 0x00000800
> +
> +#define REG_A6XX_PC_PRIMITIVE_CNTL_3 0x00009b03
> +#define A6XX_PC_PRIMITIVE_CNTL_3_STRIDE_IN_VPC__MASK 0x000000ff
> +#define A6XX_PC_PRIMITIVE_CNTL_3_STRIDE_IN_VPC__SHIFT 0
> +static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_3_STRIDE_IN_VPC(uint32_t val)
> +{
> + return ((val) << A6XX_PC_PRIMITIVE_CNTL_3_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_3_STRIDE_IN_VPC__MASK;
> +}
> +#define A6XX_PC_PRIMITIVE_CNTL_3_PSIZE 0x00000100
> +
> +#define REG_A6XX_PC_PRIMITIVE_CNTL_4 0x00009b04
> +#define A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC__MASK 0x000000ff
> +#define A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC__SHIFT 0
> +static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC(uint32_t val)
> +{
> + return ((val) << A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC__MASK;
> +}
> +#define A6XX_PC_PRIMITIVE_CNTL_4_PSIZE 0x00000100
> +
> +#define REG_A6XX_PC_PRIMITIVE_CNTL_5 0x00009b05
> +#define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK 0x000000ff
> +#define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT 0
> +static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(uint32_t val)
> +{
> + return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK;
> +}
> +#define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK 0x00007c00
> +#define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT 10
> +static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(uint32_t val)
> +{
> + return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK;
> +}
> +#define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK 0x00030000
> +#define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT 16
> +static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val)
> +{
> + return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK;
> +}
> +
> +#define REG_A6XX_PC_PRIMITIVE_CNTL_6 0x00009b06
> +#define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK 0x000001ff
> +#define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT 0
> +static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(uint32_t val)
> +{
> + return ((val) << A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK;
> +}
>
> #define REG_A6XX_PC_UNKNOWN_9B07 0x00009b07
>
> @@ -4079,14 +4772,56 @@ static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(uint32_t val)
>
> #define REG_A6XX_PC_TESSFACTOR_ADDR_HI 0x00009e09
>
> +#define REG_A6XX_PC_VSTREAM_CONTROL 0x00009e11
> +#define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK 0x003f0000
> +#define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT 16
> +static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_SIZE(uint32_t val)
> +{
> + return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK;
> +}
> +#define A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK 0x07c00000
> +#define A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT 22
> +static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_N(uint32_t val)
> +{
> + return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK;
> +}
> +
> +#define REG_A6XX_PC_BIN_DATA_ADDR2_LO 0x00009e12
> +
> +#define REG_A6XX_PC_BIN_DATA_ADDR2_HI 0x00009e13
> +
> +#define REG_A6XX_PC_BIN_DATA_ADDR_LO 0x00009e14
> +
> +#define REG_A6XX_PC_BIN_DATA_ADDR_HI 0x00009e15
> +
> +#define REG_A6XX_PC_2D_EVENT_CMD 0x00009c00
> +#define A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK 0x0000ff00
> +#define A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT 8
> +static inline uint32_t A6XX_PC_2D_EVENT_CMD_STATE_ID(uint32_t val)
> +{
> + return ((val) << A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK;
> +}
> +#define A6XX_PC_2D_EVENT_CMD_EVENT__MASK 0x0000007f
> +#define A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT 0
> +static inline uint32_t A6XX_PC_2D_EVENT_CMD_EVENT(enum vgt_event_type val)
> +{
> + return ((val) << A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_2D_EVENT_CMD_EVENT__MASK;
> +}
> +
> #define REG_A6XX_PC_UNKNOWN_9E72 0x00009e72
>
> #define REG_A6XX_VFD_CONTROL_0 0x0000a000
> -#define A6XX_VFD_CONTROL_0_VTXCNT__MASK 0x0000003f
> -#define A6XX_VFD_CONTROL_0_VTXCNT__SHIFT 0
> -static inline uint32_t A6XX_VFD_CONTROL_0_VTXCNT(uint32_t val)
> +#define A6XX_VFD_CONTROL_0_FETCH_CNT__MASK 0x0000003f
> +#define A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT 0
> +static inline uint32_t A6XX_VFD_CONTROL_0_FETCH_CNT(uint32_t val)
> {
> - return ((val) << A6XX_VFD_CONTROL_0_VTXCNT__SHIFT) & A6XX_VFD_CONTROL_0_VTXCNT__MASK;
> + return ((val) << A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT) & A6XX_VFD_CONTROL_0_FETCH_CNT__MASK;
> +}
> +#define A6XX_VFD_CONTROL_0_DECODE_CNT__MASK 0x00003f00
> +#define A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT 8
> +static inline uint32_t A6XX_VFD_CONTROL_0_DECODE_CNT(uint32_t val)
> +{
> + return ((val) << A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT) & A6XX_VFD_CONTROL_0_DECODE_CNT__MASK;
> }
>
> #define REG_A6XX_VFD_CONTROL_1 0x0000a001
> @@ -4110,19 +4845,25 @@ static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val)
> }
>
> #define REG_A6XX_VFD_CONTROL_2 0x0000a002
> -#define A6XX_VFD_CONTROL_2_REGID_PATCHID__MASK 0x000000ff
> -#define A6XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT 0
> -static inline uint32_t A6XX_VFD_CONTROL_2_REGID_PATCHID(uint32_t val)
> +#define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__MASK 0x000000ff
> +#define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__SHIFT 0
> +static inline uint32_t A6XX_VFD_CONTROL_2_REGID_HSPATCHID(uint32_t val)
> +{
> + return ((val) << A6XX_VFD_CONTROL_2_REGID_HSPATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_HSPATCHID__MASK;
> +}
> +#define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK 0x0000ff00
> +#define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT 8
> +static inline uint32_t A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val)
> {
> - return ((val) << A6XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_PATCHID__MASK;
> + return ((val) << A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK;
> }
>
> #define REG_A6XX_VFD_CONTROL_3 0x0000a003
> -#define A6XX_VFD_CONTROL_3_REGID_PATCHID__MASK 0x0000ff00
> -#define A6XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT 8
> -static inline uint32_t A6XX_VFD_CONTROL_3_REGID_PATCHID(uint32_t val)
> +#define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__MASK 0x0000ff00
> +#define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__SHIFT 8
> +static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSPATCHID(uint32_t val)
> {
> - return ((val) << A6XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_PATCHID__MASK;
> + return ((val) << A6XX_VFD_CONTROL_3_REGID_DSPATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSPATCHID__MASK;
> }
> #define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
> #define A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16
> @@ -4140,15 +4881,24 @@ static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
> #define REG_A6XX_VFD_CONTROL_4 0x0000a004
>
> #define REG_A6XX_VFD_CONTROL_5 0x0000a005
> +#define A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK 0x000000ff
> +#define A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT 0
> +static inline uint32_t A6XX_VFD_CONTROL_5_REGID_GSHEADER(uint32_t val)
> +{
> + return ((val) << A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT) & A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK;
> +}
>
> #define REG_A6XX_VFD_CONTROL_6 0x0000a006
> +#define A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU 0x00000001
>
> #define REG_A6XX_VFD_MODE_CNTL 0x0000a007
> #define A6XX_VFD_MODE_CNTL_BINNING_PASS 0x00000001
>
> #define REG_A6XX_VFD_UNKNOWN_A008 0x0000a008
>
> -#define REG_A6XX_VFD_UNKNOWN_A009 0x0000a009
> +#define REG_A6XX_VFD_ADD_OFFSET 0x0000a009
> +#define A6XX_VFD_ADD_OFFSET_VERTEX 0x00000001
> +#define A6XX_VFD_ADD_OFFSET_INSTANCE 0x00000002
>
> #define REG_A6XX_VFD_INDEX_OFFSET 0x0000a00e
>
> @@ -4156,6 +4906,8 @@ static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
>
> static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
>
> +static inline uint32_t REG_A6XX_VFD_FETCH_BASE(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
> +
> static inline uint32_t REG_A6XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
>
> static inline uint32_t REG_A6XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000a011 + 0x4*i0; }
> @@ -4173,10 +4925,16 @@ static inline uint32_t A6XX_VFD_DECODE_INSTR_IDX(uint32_t val)
> {
> return ((val) << A6XX_VFD_DECODE_INSTR_IDX__SHIFT) & A6XX_VFD_DECODE_INSTR_IDX__MASK;
> }
> +#define A6XX_VFD_DECODE_INSTR_OFFSET__MASK 0x0001ffe0
> +#define A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT 5
> +static inline uint32_t A6XX_VFD_DECODE_INSTR_OFFSET(uint32_t val)
> +{
> + return ((val) << A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT) & A6XX_VFD_DECODE_INSTR_OFFSET__MASK;
> +}
> #define A6XX_VFD_DECODE_INSTR_INSTANCED 0x00020000
> #define A6XX_VFD_DECODE_INSTR_FORMAT__MASK 0x0ff00000
> #define A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20
> -static inline uint32_t A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_vtx_fmt val)
> +static inline uint32_t A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_format val)
> {
> return ((val) << A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A6XX_VFD_DECODE_INSTR_FORMAT__MASK;
> }
> @@ -4209,8 +4967,40 @@ static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)
>
> #define REG_A6XX_SP_UNKNOWN_A0F8 0x0000a0f8
>
> +#define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800
> +#define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
> +#define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
> +static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
> +{
> + return ((val) << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
> +}
> +#define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
> +#define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
> +static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
> +{
> + return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
> +}
> +#define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
> +#define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 14
> +static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
> +{
> + return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;
> +}
> +#define A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
> +#define A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20
> +static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
> +{
> + return ((val) << A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
> +}
> +#define A6XX_SP_VS_CTRL_REG0_VARYING 0x00400000
> +#define A6XX_SP_VS_CTRL_REG0_DIFF_FINE 0x00800000
> +#define A6XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x04000000
> +#define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x80000000
> +
> +#define REG_A6XX_SP_VS_BRANCH_COND 0x0000a801
> +
> #define REG_A6XX_SP_PRIMITIVE_CNTL 0x0000a802
> -#define A6XX_SP_PRIMITIVE_CNTL_VSOUT__MASK 0x0000001f
> +#define A6XX_SP_PRIMITIVE_CNTL_VSOUT__MASK 0x0000003f
> #define A6XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT 0
> static inline uint32_t A6XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val)
> {
> @@ -4273,35 +5063,6 @@ static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
> return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
> }
>
> -#define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800
> -#define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
> -#define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
> -static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
> -{
> - return ((val) << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
> -}
> -#define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
> -#define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
> -static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
> -{
> - return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
> -}
> -#define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
> -#define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 14
> -static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
> -{
> - return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;
> -}
> -#define A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
> -#define A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20
> -static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
> -{
> - return ((val) << A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
> -}
> -#define A6XX_SP_VS_CTRL_REG0_VARYING 0x00400000
> -#define A6XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x04000000
> -#define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x80000000
> -
> #define REG_A6XX_SP_UNKNOWN_A81B 0x0000a81b
>
> #define REG_A6XX_SP_VS_OBJ_START_LO 0x0000a81c
> @@ -4311,6 +5072,10 @@ static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
> #define REG_A6XX_SP_VS_TEX_COUNT 0x0000a822
>
> #define REG_A6XX_SP_VS_CONFIG 0x0000a823
> +#define A6XX_SP_VS_CONFIG_BINDLESS_TEX 0x00000001
> +#define A6XX_SP_VS_CONFIG_BINDLESS_SAMP 0x00000002
> +#define A6XX_SP_VS_CONFIG_BINDLESS_IBO 0x00000004
> +#define A6XX_SP_VS_CONFIG_BINDLESS_UBO 0x00000008
> #define A6XX_SP_VS_CONFIG_ENABLED 0x00000100
> #define A6XX_SP_VS_CONFIG_NTEX__MASK 0x0001fe00
> #define A6XX_SP_VS_CONFIG_NTEX__SHIFT 9
> @@ -4318,12 +5083,18 @@ static inline uint32_t A6XX_SP_VS_CONFIG_NTEX(uint32_t val)
> {
> return ((val) << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK;
> }
> -#define A6XX_SP_VS_CONFIG_NSAMP__MASK 0x01fe0000
> +#define A6XX_SP_VS_CONFIG_NSAMP__MASK 0x003e0000
> #define A6XX_SP_VS_CONFIG_NSAMP__SHIFT 17
> static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val)
> {
> return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK;
> }
> +#define A6XX_SP_VS_CONFIG_NIBO__MASK 0x3fc00000
> +#define A6XX_SP_VS_CONFIG_NIBO__SHIFT 22
> +static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val)
> +{
> + return ((val) << A6XX_SP_VS_CONFIG_NIBO__SHIFT) & A6XX_SP_VS_CONFIG_NIBO__MASK;
> +}
>
> #define REG_A6XX_SP_VS_INSTRLEN 0x0000a824
>
> @@ -4353,11 +5124,14 @@ static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
> return ((val) << A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK;
> }
> #define A6XX_SP_HS_CTRL_REG0_VARYING 0x00400000
> +#define A6XX_SP_HS_CTRL_REG0_DIFF_FINE 0x00800000
> #define A6XX_SP_HS_CTRL_REG0_PIXLODENABLE 0x04000000
> #define A6XX_SP_HS_CTRL_REG0_MERGEDREGS 0x80000000
>
> #define REG_A6XX_SP_HS_UNKNOWN_A831 0x0000a831
>
> +#define REG_A6XX_SP_HS_UNKNOWN_A833 0x0000a833
> +
> #define REG_A6XX_SP_HS_OBJ_START_LO 0x0000a834
>
> #define REG_A6XX_SP_HS_OBJ_START_HI 0x0000a835
> @@ -4365,6 +5139,10 @@ static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
> #define REG_A6XX_SP_HS_TEX_COUNT 0x0000a83a
>
> #define REG_A6XX_SP_HS_CONFIG 0x0000a83b
> +#define A6XX_SP_HS_CONFIG_BINDLESS_TEX 0x00000001
> +#define A6XX_SP_HS_CONFIG_BINDLESS_SAMP 0x00000002
> +#define A6XX_SP_HS_CONFIG_BINDLESS_IBO 0x00000004
> +#define A6XX_SP_HS_CONFIG_BINDLESS_UBO 0x00000008
> #define A6XX_SP_HS_CONFIG_ENABLED 0x00000100
> #define A6XX_SP_HS_CONFIG_NTEX__MASK 0x0001fe00
> #define A6XX_SP_HS_CONFIG_NTEX__SHIFT 9
> @@ -4372,12 +5150,18 @@ static inline uint32_t A6XX_SP_HS_CONFIG_NTEX(uint32_t val)
> {
> return ((val) << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK;
> }
> -#define A6XX_SP_HS_CONFIG_NSAMP__MASK 0x01fe0000
> +#define A6XX_SP_HS_CONFIG_NSAMP__MASK 0x003e0000
> #define A6XX_SP_HS_CONFIG_NSAMP__SHIFT 17
> static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val)
> {
> return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK;
> }
> +#define A6XX_SP_HS_CONFIG_NIBO__MASK 0x3fc00000
> +#define A6XX_SP_HS_CONFIG_NIBO__SHIFT 22
> +static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val)
> +{
> + return ((val) << A6XX_SP_HS_CONFIG_NIBO__SHIFT) & A6XX_SP_HS_CONFIG_NIBO__MASK;
> +}
>
> #define REG_A6XX_SP_HS_INSTRLEN 0x0000a83c
>
> @@ -4407,9 +5191,76 @@ static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
> return ((val) << A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK;
> }
> #define A6XX_SP_DS_CTRL_REG0_VARYING 0x00400000
> +#define A6XX_SP_DS_CTRL_REG0_DIFF_FINE 0x00800000
> #define A6XX_SP_DS_CTRL_REG0_PIXLODENABLE 0x04000000
> #define A6XX_SP_DS_CTRL_REG0_MERGEDREGS 0x80000000
>
> +#define REG_A6XX_SP_DS_PRIMITIVE_CNTL 0x0000a842
> +#define A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT__MASK 0x0000001f
> +#define A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT__SHIFT 0
> +static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT(uint32_t val)
> +{
> + return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT__MASK;
> +}
> +
> +static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; }
> +
> +static inline uint32_t REG_A6XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000a843 + 0x1*i0; }
> +#define A6XX_SP_DS_OUT_REG_A_REGID__MASK 0x000000ff
> +#define A6XX_SP_DS_OUT_REG_A_REGID__SHIFT 0
> +static inline uint32_t A6XX_SP_DS_OUT_REG_A_REGID(uint32_t val)
> +{
> + return ((val) << A6XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_A_REGID__MASK;
> +}
> +#define A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00000f00
> +#define A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 8
> +static inline uint32_t A6XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)
> +{
> + return ((val) << A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK;
> +}
> +#define A6XX_SP_DS_OUT_REG_B_REGID__MASK 0x00ff0000
> +#define A6XX_SP_DS_OUT_REG_B_REGID__SHIFT 16
> +static inline uint32_t A6XX_SP_DS_OUT_REG_B_REGID(uint32_t val)
> +{
> + return ((val) << A6XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_B_REGID__MASK;
> +}
> +#define A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x0f000000
> +#define A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 24
> +static inline uint32_t A6XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)
> +{
> + return ((val) << A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK;
> +}
> +
> +static inline uint32_t REG_A6XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000a853 + 0x1*i0; }
> +
> +static inline uint32_t REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000a853 + 0x1*i0; }
> +#define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
> +#define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0
> +static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)
> +{
> + return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK;
> +}
> +#define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
> +#define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8
> +static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)
> +{
> + return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK;
> +}
> +#define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
> +#define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16
> +static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)
> +{
> + return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK;
> +}
> +#define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
> +#define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24
> +static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)
> +{
> + return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;
> +}
> +
> +#define REG_A6XX_SP_DS_UNKNOWN_A85B 0x0000a85b
> +
> #define REG_A6XX_SP_DS_OBJ_START_LO 0x0000a85c
>
> #define REG_A6XX_SP_DS_OBJ_START_HI 0x0000a85d
> @@ -4417,6 +5268,10 @@ static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
> #define REG_A6XX_SP_DS_TEX_COUNT 0x0000a862
>
> #define REG_A6XX_SP_DS_CONFIG 0x0000a863
> +#define A6XX_SP_DS_CONFIG_BINDLESS_TEX 0x00000001
> +#define A6XX_SP_DS_CONFIG_BINDLESS_SAMP 0x00000002
> +#define A6XX_SP_DS_CONFIG_BINDLESS_IBO 0x00000004
> +#define A6XX_SP_DS_CONFIG_BINDLESS_UBO 0x00000008
> #define A6XX_SP_DS_CONFIG_ENABLED 0x00000100
> #define A6XX_SP_DS_CONFIG_NTEX__MASK 0x0001fe00
> #define A6XX_SP_DS_CONFIG_NTEX__SHIFT 9
> @@ -4424,12 +5279,18 @@ static inline uint32_t A6XX_SP_DS_CONFIG_NTEX(uint32_t val)
> {
> return ((val) << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK;
> }
> -#define A6XX_SP_DS_CONFIG_NSAMP__MASK 0x01fe0000
> +#define A6XX_SP_DS_CONFIG_NSAMP__MASK 0x003e0000
> #define A6XX_SP_DS_CONFIG_NSAMP__SHIFT 17
> static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val)
> {
> return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK;
> }
> +#define A6XX_SP_DS_CONFIG_NIBO__MASK 0x3fc00000
> +#define A6XX_SP_DS_CONFIG_NIBO__SHIFT 22
> +static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val)
> +{
> + return ((val) << A6XX_SP_DS_CONFIG_NIBO__SHIFT) & A6XX_SP_DS_CONFIG_NIBO__MASK;
> +}
>
> #define REG_A6XX_SP_DS_INSTRLEN 0x0000a864
>
> @@ -4459,10 +5320,83 @@ static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
> return ((val) << A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK;
> }
> #define A6XX_SP_GS_CTRL_REG0_VARYING 0x00400000
> +#define A6XX_SP_GS_CTRL_REG0_DIFF_FINE 0x00800000
> #define A6XX_SP_GS_CTRL_REG0_PIXLODENABLE 0x04000000
> #define A6XX_SP_GS_CTRL_REG0_MERGEDREGS 0x80000000
>
> -#define REG_A6XX_SP_GS_UNKNOWN_A871 0x0000a871
> +#define REG_A6XX_SP_GS_PRIM_SIZE 0x0000a871
> +
> +#define REG_A6XX_SP_GS_BRANCH_COND 0x0000a872
> +
> +#define REG_A6XX_SP_PRIMITIVE_CNTL_GS 0x0000a873
> +#define A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT__MASK 0x0000003f
> +#define A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT__SHIFT 0
> +static inline uint32_t A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(uint32_t val)
> +{
> + return ((val) << A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT__SHIFT) & A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT__MASK;
> +}
> +#define A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID__MASK 0x00003fc0
> +#define A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID__SHIFT 6
> +static inline uint32_t A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(uint32_t val)
> +{
> + return ((val) << A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID__SHIFT) & A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID__MASK;
> +}
> +
> +static inline uint32_t REG_A6XX_SP_GS_OUT(uint32_t i0) { return 0x0000a874 + 0x1*i0; }
> +
> +static inline uint32_t REG_A6XX_SP_GS_OUT_REG(uint32_t i0) { return 0x0000a874 + 0x1*i0; }
> +#define A6XX_SP_GS_OUT_REG_A_REGID__MASK 0x000000ff
> +#define A6XX_SP_GS_OUT_REG_A_REGID__SHIFT 0
> +static inline uint32_t A6XX_SP_GS_OUT_REG_A_REGID(uint32_t val)
> +{
> + return ((val) << A6XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_A_REGID__MASK;
> +}
> +#define A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00000f00
> +#define A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 8
> +static inline uint32_t A6XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val)
> +{
> + return ((val) << A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK;
> +}
> +#define A6XX_SP_GS_OUT_REG_B_REGID__MASK 0x00ff0000
> +#define A6XX_SP_GS_OUT_REG_B_REGID__SHIFT 16
> +static inline uint32_t A6XX_SP_GS_OUT_REG_B_REGID(uint32_t val)
> +{
> + return ((val) << A6XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_B_REGID__MASK;
> +}
> +#define A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x0f000000
> +#define A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 24
> +static inline uint32_t A6XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val)
> +{
> + return ((val) << A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK;
> +}
> +
> +static inline uint32_t REG_A6XX_SP_GS_VPC_DST(uint32_t i0) { return 0x0000a884 + 0x1*i0; }
> +
> +static inline uint32_t REG_A6XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x0000a884 + 0x1*i0; }
> +#define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
> +#define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0
> +static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val)
> +{
> + return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK;
> +}
> +#define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
> +#define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8
> +static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val)
> +{
> + return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK;
> +}
> +#define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
> +#define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16
> +static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val)
> +{
> + return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK;
> +}
> +#define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
> +#define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24
> +static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)
> +{
> + return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK;
> +}
>
> #define REG_A6XX_SP_GS_OBJ_START_LO 0x0000a88d
>
> @@ -4471,6 +5405,10 @@ static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
> #define REG_A6XX_SP_GS_TEX_COUNT 0x0000a893
>
> #define REG_A6XX_SP_GS_CONFIG 0x0000a894
> +#define A6XX_SP_GS_CONFIG_BINDLESS_TEX 0x00000001
> +#define A6XX_SP_GS_CONFIG_BINDLESS_SAMP 0x00000002
> +#define A6XX_SP_GS_CONFIG_BINDLESS_IBO 0x00000004
> +#define A6XX_SP_GS_CONFIG_BINDLESS_UBO 0x00000008
> #define A6XX_SP_GS_CONFIG_ENABLED 0x00000100
> #define A6XX_SP_GS_CONFIG_NTEX__MASK 0x0001fe00
> #define A6XX_SP_GS_CONFIG_NTEX__SHIFT 9
> @@ -4478,12 +5416,18 @@ static inline uint32_t A6XX_SP_GS_CONFIG_NTEX(uint32_t val)
> {
> return ((val) << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK;
> }
> -#define A6XX_SP_GS_CONFIG_NSAMP__MASK 0x01fe0000
> +#define A6XX_SP_GS_CONFIG_NSAMP__MASK 0x003e0000
> #define A6XX_SP_GS_CONFIG_NSAMP__SHIFT 17
> static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val)
> {
> return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK;
> }
> +#define A6XX_SP_GS_CONFIG_NIBO__MASK 0x3fc00000
> +#define A6XX_SP_GS_CONFIG_NIBO__SHIFT 22
> +static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val)
> +{
> + return ((val) << A6XX_SP_GS_CONFIG_NIBO__SHIFT) & A6XX_SP_GS_CONFIG_NIBO__MASK;
> +}
>
> #define REG_A6XX_SP_GS_INSTRLEN 0x0000a895
>
> @@ -4545,9 +5489,12 @@ static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
> return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
> }
> #define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000
> +#define A6XX_SP_FS_CTRL_REG0_DIFF_FINE 0x00800000
> #define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000
> #define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000
>
> +#define REG_A6XX_SP_FS_BRANCH_COND 0x0000a981
> +
> #define REG_A6XX_SP_UNKNOWN_A982 0x0000a982
>
> #define REG_A6XX_SP_FS_OBJ_START_LO 0x0000a983
> @@ -4557,6 +5504,7 @@ static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
> #define REG_A6XX_SP_BLEND_CNTL 0x0000a989
> #define A6XX_SP_BLEND_CNTL_ENABLED 0x00000001
> #define A6XX_SP_BLEND_CNTL_UNK8 0x00000100
> +#define A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200
> #define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
>
> #define REG_A6XX_SP_SRGB_CNTL 0x0000a98a
> @@ -4620,12 +5568,19 @@ static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val)
> }
>
> #define REG_A6XX_SP_FS_OUTPUT_CNTL0 0x0000a98c
> +#define A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE 0x00000001
> #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK 0x0000ff00
> #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT 8
> static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val)
> {
> return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK;
> }
> +#define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK 0x00ff0000
> +#define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT 16
> +static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(uint32_t val)
> +{
> + return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK;
> +}
>
> #define REG_A6XX_SP_FS_OUTPUT_CNTL1 0x0000a98d
> #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f
> @@ -4640,19 +5595,95 @@ static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1
> static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
> #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff
> #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0
> -static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_color_fmt val)
> +static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_format val)
> {
> return ((val) << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK;
> }
> #define A6XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100
> #define A6XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200
>
> -#define REG_A6XX_SP_UNKNOWN_A99E 0x0000a99e
> +#define REG_A6XX_SP_FS_PREFETCH_CNTL 0x0000a99e
> +#define A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK 0x00000007
> +#define A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT 0
> +static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_COUNT(uint32_t val)
> +{
> + return ((val) << A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK;
> +}
> +#define A6XX_SP_FS_PREFETCH_CNTL_UNK3 0x00000008
> +#define A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK 0x00000ff0
> +#define A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT 4
> +static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK4(uint32_t val)
> +{
> + return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK;
> +}
> +
> +static inline uint32_t REG_A6XX_SP_FS_PREFETCH(uint32_t i0) { return 0x0000a99f + 0x1*i0; }
> +
> +static inline uint32_t REG_A6XX_SP_FS_PREFETCH_CMD(uint32_t i0) { return 0x0000a99f + 0x1*i0; }
> +#define A6XX_SP_FS_PREFETCH_CMD_SRC__MASK 0x0000007f
> +#define A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT 0
> +static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val)
> +{
> + return ((val) << A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SRC__MASK;
> +}
> +#define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK 0x00000780
> +#define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT 7
> +static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(uint32_t val)
> +{
> + return ((val) << A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK;
> +}
> +#define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK 0x0000f800
> +#define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT 11
> +static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_TEX_ID(uint32_t val)
> +{
> + return ((val) << A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK;
> +}
> +#define A6XX_SP_FS_PREFETCH_CMD_DST__MASK 0x003f0000
> +#define A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT 16
> +static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_DST(uint32_t val)
> +{
> + return ((val) << A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_DST__MASK;
> +}
> +#define A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK 0x03c00000
> +#define A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT 22
> +static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_WRMASK(uint32_t val)
> +{
> + return ((val) << A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK;
> +}
> +#define A6XX_SP_FS_PREFETCH_CMD_HALF 0x04000000
> +#define A6XX_SP_FS_PREFETCH_CMD_CMD__MASK 0xf8000000
> +#define A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT 27
> +static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_CMD(uint32_t val)
> +{
> + return ((val) << A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_CMD__MASK;
> +}
> +
> +static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }
> +
> +static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }
> +#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK 0x000000ff
> +#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT 0
> +static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(uint32_t val)
> +{
> + return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK;
> +}
> +#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK 0x00ff0000
> +#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT 16
> +static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val)
> +{
> + return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK;
> +}
>
> #define REG_A6XX_SP_FS_TEX_COUNT 0x0000a9a7
>
> #define REG_A6XX_SP_UNKNOWN_A9A8 0x0000a9a8
>
> +#define REG_A6XX_SP_CS_UNKNOWN_A9B1 0x0000a9b1
> +
> +#define REG_A6XX_SP_CS_UNKNOWN_A9B3 0x0000a9b3
> +
> +#define REG_A6XX_SP_CS_TEX_COUNT 0x0000a9ba
> +
> #define REG_A6XX_SP_FS_TEX_SAMP_LO 0x0000a9e0
>
> #define REG_A6XX_SP_FS_TEX_SAMP_HI 0x0000a9e1
> @@ -4669,6 +5700,10 @@ static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_color_fmt val)
>
> #define REG_A6XX_SP_CS_TEX_CONST_HI 0x0000a9e7
>
> +static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
> +
> +static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
> +
> static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
>
> static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
> @@ -4706,6 +5741,7 @@ static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
> return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
> }
> #define A6XX_SP_CS_CTRL_REG0_VARYING 0x00400000
> +#define A6XX_SP_CS_CTRL_REG0_DIFF_FINE 0x00800000
> #define A6XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x04000000
> #define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000
>
> @@ -4713,11 +5749,46 @@ static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
>
> #define REG_A6XX_SP_CS_OBJ_START_HI 0x0000a9b5
>
> +#define REG_A6XX_SP_CS_CONFIG 0x0000a9bb
> +#define A6XX_SP_CS_CONFIG_BINDLESS_TEX 0x00000001
> +#define A6XX_SP_CS_CONFIG_BINDLESS_SAMP 0x00000002
> +#define A6XX_SP_CS_CONFIG_BINDLESS_IBO 0x00000004
> +#define A6XX_SP_CS_CONFIG_BINDLESS_UBO 0x00000008
> +#define A6XX_SP_CS_CONFIG_ENABLED 0x00000100
> +#define A6XX_SP_CS_CONFIG_NTEX__MASK 0x0001fe00
> +#define A6XX_SP_CS_CONFIG_NTEX__SHIFT 9
> +static inline uint32_t A6XX_SP_CS_CONFIG_NTEX(uint32_t val)
> +{
> + return ((val) << A6XX_SP_CS_CONFIG_NTEX__SHIFT) & A6XX_SP_CS_CONFIG_NTEX__MASK;
> +}
> +#define A6XX_SP_CS_CONFIG_NSAMP__MASK 0x003e0000
> +#define A6XX_SP_CS_CONFIG_NSAMP__SHIFT 17
> +static inline uint32_t A6XX_SP_CS_CONFIG_NSAMP(uint32_t val)
> +{
> + return ((val) << A6XX_SP_CS_CONFIG_NSAMP__SHIFT) & A6XX_SP_CS_CONFIG_NSAMP__MASK;
> +}
> +#define A6XX_SP_CS_CONFIG_NIBO__MASK 0x3fc00000
> +#define A6XX_SP_CS_CONFIG_NIBO__SHIFT 22
> +static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val)
> +{
> + return ((val) << A6XX_SP_CS_CONFIG_NIBO__SHIFT) & A6XX_SP_CS_CONFIG_NIBO__MASK;
> +}
> +
> #define REG_A6XX_SP_CS_INSTRLEN 0x0000a9bc
>
> +#define REG_A6XX_SP_CS_IBO_LO 0x0000a9f2
> +
> +#define REG_A6XX_SP_CS_IBO_HI 0x0000a9f3
> +
> +#define REG_A6XX_SP_CS_IBO_COUNT 0x0000aa00
> +
> #define REG_A6XX_SP_UNKNOWN_AB00 0x0000ab00
>
> #define REG_A6XX_SP_FS_CONFIG 0x0000ab04
> +#define A6XX_SP_FS_CONFIG_BINDLESS_TEX 0x00000001
> +#define A6XX_SP_FS_CONFIG_BINDLESS_SAMP 0x00000002
> +#define A6XX_SP_FS_CONFIG_BINDLESS_IBO 0x00000004
> +#define A6XX_SP_FS_CONFIG_BINDLESS_UBO 0x00000008
> #define A6XX_SP_FS_CONFIG_ENABLED 0x00000100
> #define A6XX_SP_FS_CONFIG_NTEX__MASK 0x0001fe00
> #define A6XX_SP_FS_CONFIG_NTEX__SHIFT 9
> @@ -4725,18 +5796,48 @@ static inline uint32_t A6XX_SP_FS_CONFIG_NTEX(uint32_t val)
> {
> return ((val) << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK;
> }
> -#define A6XX_SP_FS_CONFIG_NSAMP__MASK 0x01fe0000
> +#define A6XX_SP_FS_CONFIG_NSAMP__MASK 0x003e0000
> #define A6XX_SP_FS_CONFIG_NSAMP__SHIFT 17
> static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val)
> {
> return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK;
> }
> +#define A6XX_SP_FS_CONFIG_NIBO__MASK 0x3fc00000
> +#define A6XX_SP_FS_CONFIG_NIBO__SHIFT 22
> +static inline uint32_t A6XX_SP_FS_CONFIG_NIBO(uint32_t val)
> +{
> + return ((val) << A6XX_SP_FS_CONFIG_NIBO__SHIFT) & A6XX_SP_FS_CONFIG_NIBO__MASK;
> +}
>
> #define REG_A6XX_SP_FS_INSTRLEN 0x0000ab05
>
> -#define REG_A6XX_SP_UNKNOWN_AB20 0x0000ab20
> +static inline uint32_t REG_A6XX_SP_BINDLESS_BASE(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }
>
> -#define REG_A6XX_SP_UNKNOWN_ACC0 0x0000acc0
> +static inline uint32_t REG_A6XX_SP_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }
> +
> +#define REG_A6XX_SP_IBO_LO 0x0000ab1a
> +
> +#define REG_A6XX_SP_IBO_HI 0x0000ab1b
> +
> +#define REG_A6XX_SP_IBO_COUNT 0x0000ab20
> +
> +#define REG_A6XX_SP_2D_SRC_FORMAT 0x0000acc0
> +#define A6XX_SP_2D_SRC_FORMAT_NORM 0x00000001
> +#define A6XX_SP_2D_SRC_FORMAT_SINT 0x00000002
> +#define A6XX_SP_2D_SRC_FORMAT_UINT 0x00000004
> +#define A6XX_SP_2D_SRC_FORMAT_COLOR_FORMAT__MASK 0x000007f8
> +#define A6XX_SP_2D_SRC_FORMAT_COLOR_FORMAT__SHIFT 3
> +static inline uint32_t A6XX_SP_2D_SRC_FORMAT_COLOR_FORMAT(enum a6xx_format val)
> +{
> + return ((val) << A6XX_SP_2D_SRC_FORMAT_COLOR_FORMAT__SHIFT) & A6XX_SP_2D_SRC_FORMAT_COLOR_FORMAT__MASK;
> +}
> +#define A6XX_SP_2D_SRC_FORMAT_SRGB 0x00000800
> +#define A6XX_SP_2D_SRC_FORMAT_MASK__MASK 0x0000f000
> +#define A6XX_SP_2D_SRC_FORMAT_MASK__SHIFT 12
> +static inline uint32_t A6XX_SP_2D_SRC_FORMAT_MASK(uint32_t val)
> +{
> + return ((val) << A6XX_SP_2D_SRC_FORMAT_MASK__SHIFT) & A6XX_SP_2D_SRC_FORMAT_MASK__MASK;
> +}
>
> #define REG_A6XX_SP_UNKNOWN_AE00 0x0000ae00
>
> @@ -4746,6 +5847,8 @@ static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val)
>
> #define REG_A6XX_SP_UNKNOWN_AE0F 0x0000ae0f
>
> +#define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR 0x0000b180
> +
> #define REG_A6XX_SP_UNKNOWN_B182 0x0000b182
>
> #define REG_A6XX_SP_UNKNOWN_B183 0x0000b183
> @@ -4767,18 +5870,121 @@ static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples
> }
> #define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
>
> +#define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR 0x0000b302
> +
> #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO 0x0000b302
>
> #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_HI 0x0000b303
>
> -#define REG_A6XX_SP_TP_UNKNOWN_B304 0x0000b304
> +#define REG_A6XX_SP_TP_SAMPLE_CONFIG 0x0000b304
> +#define A6XX_SP_TP_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002
> +
> +#define REG_A6XX_SP_TP_SAMPLE_LOCATION_0 0x0000b305
> +#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f
> +#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0
> +static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
> +}
> +#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0
> +#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4
> +static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
> +}
> +#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00
> +#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8
> +static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
> +}
> +#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000
> +#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12
> +static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
> +}
> +#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000
> +#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16
> +static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
> +}
> +#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000
> +#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20
> +static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
> +}
> +#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000
> +#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24
> +static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
> +}
> +#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000
> +#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28
> +static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
> +}
> +
> +#define REG_A6XX_SP_TP_SAMPLE_LOCATION_1 0x0000b306
> +#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f
> +#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0
> +static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
> +}
> +#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0
> +#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4
> +static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
> +}
> +#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00
> +#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8
> +static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
> +}
> +#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000
> +#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12
> +static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
> +}
> +#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000
> +#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16
> +static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
> +}
> +#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000
> +#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20
> +static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
> +}
> +#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000
> +#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24
> +static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
> +}
> +#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000
> +#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28
> +static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
> +{
> + return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
> +}
>
> #define REG_A6XX_SP_TP_UNKNOWN_B309 0x0000b309
>
> #define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0
> #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
> #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
> -static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
> +static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val)
> {
> return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK;
> }
> @@ -4795,7 +6001,17 @@ static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap va
> return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK;
> }
> #define A6XX_SP_PS_2D_SRC_INFO_FLAGS 0x00001000
> +#define A6XX_SP_PS_2D_SRC_INFO_SRGB 0x00002000
> +#define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK 0x0000c000
> +#define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT 14
> +static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val)
> +{
> + return ((val) << A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK;
> +}
> #define A6XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000
> +#define A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE 0x00040000
> +#define A6XX_SP_PS_2D_SRC_INFO_UNK20 0x00100000
> +#define A6XX_SP_PS_2D_SRC_INFO_UNK22 0x00400000
>
> #define REG_A6XX_SP_PS_2D_SRC_SIZE 0x0000b4c1
> #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff
> @@ -4815,6 +6031,8 @@ static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val)
>
> #define REG_A6XX_SP_PS_2D_SRC_HI 0x0000b4c3
>
> +#define REG_A6XX_SP_PS_2D_SRC 0x0000b4c2
> +
> #define REG_A6XX_SP_PS_2D_SRC_PITCH 0x0000b4c4
> #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x01fffe00
> #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9
> @@ -4827,6 +6045,22 @@ static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val)
>
> #define REG_A6XX_SP_PS_2D_SRC_FLAGS_HI 0x0000b4cb
>
> +#define REG_A6XX_SP_PS_2D_SRC_FLAGS 0x0000b4ca
> +
> +#define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b4cc
> +#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__MASK 0x000007ff
> +#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__SHIFT 0
> +static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH(uint32_t val)
> +{
> + return ((val >> 6) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__MASK;
> +}
> +#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__MASK 0x003ff800
> +#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__SHIFT 11
> +static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH(uint32_t val)
> +{
> + return ((val >> 7) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__MASK;
> +}
> +
> #define REG_A6XX_SP_UNKNOWN_B600 0x0000b600
>
> #define REG_A6XX_SP_UNKNOWN_B605 0x0000b605
> @@ -4838,6 +6072,7 @@ static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val)
> {
> return ((val >> 2) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK;
> }
> +#define A6XX_HLSQ_VS_CNTL_ENABLED 0x00000100
>
> #define REG_A6XX_HLSQ_HS_CNTL 0x0000b801
> #define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK 0x000000ff
> @@ -4846,6 +6081,7 @@ static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val)
> {
> return ((val >> 2) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK;
> }
> +#define A6XX_HLSQ_HS_CNTL_ENABLED 0x00000100
>
> #define REG_A6XX_HLSQ_DS_CNTL 0x0000b802
> #define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK 0x000000ff
> @@ -4854,6 +6090,7 @@ static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val)
> {
> return ((val >> 2) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK;
> }
> +#define A6XX_HLSQ_DS_CNTL_ENABLED 0x00000100
>
> #define REG_A6XX_HLSQ_GS_CNTL 0x0000b803
> #define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK 0x000000ff
> @@ -4862,6 +6099,13 @@ static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val)
> {
> return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK;
> }
> +#define A6XX_HLSQ_GS_CNTL_ENABLED 0x00000100
> +
> +#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD 0x0000b820
> +
> +#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR 0x0000b821
> +
> +#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA 0x0000b823
>
> #define REG_A6XX_HLSQ_UNKNOWN_B980 0x0000b980
>
> @@ -4886,16 +6130,52 @@ static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)
> {
> return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK;
> }
> +#define A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK 0xff000000
> +#define A6XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT 24
> +static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SIZE(uint32_t val)
> +{
> + return ((val) << A6XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK;
> +}
>
> #define REG_A6XX_HLSQ_CONTROL_3_REG 0x0000b984
> -#define A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK 0x000000ff
> -#define A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT 0
> -static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(uint32_t val)
> +#define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff
> +#define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0
> +static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)
> +{
> + return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK;
> +}
> +#define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00
> +#define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8
> +static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)
> +{
> + return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK;
> +}
> +#define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000
> +#define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16
> +static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)
> +{
> + return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK;
> +}
> +#define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000
> +#define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24
> +static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)
> {
> - return ((val) << A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK;
> + return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK;
> }
>
> #define REG_A6XX_HLSQ_CONTROL_4_REG 0x0000b985
> +#define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff
> +#define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0
> +static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)
> +{
> + return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK;
> +}
> +#define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00
> +#define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8
> +static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)
> +{
> + return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK;
> +}
> #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000
> #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16
> static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
> @@ -4911,6 +6191,15 @@ static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
>
> #define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986
>
> +#define REG_A6XX_HLSQ_CS_CNTL 0x0000b987
> +#define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff
> +#define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT 0
> +static inline uint32_t A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val)
> +{
> + return ((val >> 2) << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK;
> +}
> +#define A6XX_HLSQ_CS_CNTL_ENABLED 0x00000100
> +
> #define REG_A6XX_HLSQ_CS_NDRANGE_0 0x0000b990
> #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003
> #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0
> @@ -5011,12 +6300,54 @@ static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)
> return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK;
> }
>
> +#define REG_A6XX_HLSQ_CS_UNKNOWN_B998 0x0000b998
> +
> #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X 0x0000b999
>
> #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000b99a
>
> #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000b99b
>
> +#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD 0x0000b9a0
> +
> +#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR 0x0000b9a1
> +
> +#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA 0x0000b9a3
> +
> +static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; }
> +
> +static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; }
> +
> +#define REG_A6XX_HLSQ_DRAW_CMD 0x0000bb00
> +#define A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK 0x000000ff
> +#define A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT 0
> +static inline uint32_t A6XX_HLSQ_DRAW_CMD_STATE_ID(uint32_t val)
> +{
> + return ((val) << A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK;
> +}
> +
> +#define REG_A6XX_HLSQ_DISPATCH_CMD 0x0000bb01
> +#define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK 0x000000ff
> +#define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT 0
> +static inline uint32_t A6XX_HLSQ_DISPATCH_CMD_STATE_ID(uint32_t val)
> +{
> + return ((val) << A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK;
> +}
> +
> +#define REG_A6XX_HLSQ_EVENT_CMD 0x0000bb02
> +#define A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK 0x00ff0000
> +#define A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT 16
> +static inline uint32_t A6XX_HLSQ_EVENT_CMD_STATE_ID(uint32_t val)
> +{
> + return ((val) << A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK;
> +}
> +#define A6XX_HLSQ_EVENT_CMD_EVENT__MASK 0x0000007f
> +#define A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT 0
> +static inline uint32_t A6XX_HLSQ_EVENT_CMD_EVENT(enum vgt_event_type val)
> +{
> + return ((val) << A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_EVENT_CMD_EVENT__MASK;
> +}
> +
> #define REG_A6XX_HLSQ_UPDATE_CNTL 0x0000bb08
>
> #define REG_A6XX_HLSQ_FS_CNTL 0x0000bb10
> @@ -5026,15 +6357,66 @@ static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val)
> {
> return ((val >> 2) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK;
> }
> +#define A6XX_HLSQ_FS_CNTL_ENABLED 0x00000100
>
> #define REG_A6XX_HLSQ_UNKNOWN_BB11 0x0000bb11
>
> +static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE(uint32_t i0) { return 0x0000bb20 + 0x2*i0; }
> +
> +static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000bb20 + 0x2*i0; }
> +
> +#define REG_A6XX_HLSQ_2D_EVENT_CMD 0x0000bd80
> +#define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK 0x0000ff00
> +#define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT 8
> +static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_STATE_ID(uint32_t val)
> +{
> + return ((val) << A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK;
> +}
> +#define A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK 0x0000007f
> +#define A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT 0
> +static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_EVENT(enum vgt_event_type val)
> +{
> + return ((val) << A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK;
> +}
> +
> #define REG_A6XX_HLSQ_UNKNOWN_BE00 0x0000be00
>
> #define REG_A6XX_HLSQ_UNKNOWN_BE01 0x0000be01
>
> #define REG_A6XX_HLSQ_UNKNOWN_BE04 0x0000be04
>
> +#define REG_A6XX_CP_EVENT_START 0x0000d600
> +#define A6XX_CP_EVENT_START_STATE_ID__MASK 0x000000ff
> +#define A6XX_CP_EVENT_START_STATE_ID__SHIFT 0
> +static inline uint32_t A6XX_CP_EVENT_START_STATE_ID(uint32_t val)
> +{
> + return ((val) << A6XX_CP_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_EVENT_START_STATE_ID__MASK;
> +}
> +
> +#define REG_A6XX_CP_EVENT_END 0x0000d601
> +#define A6XX_CP_EVENT_END_STATE_ID__MASK 0x000000ff
> +#define A6XX_CP_EVENT_END_STATE_ID__SHIFT 0
> +static inline uint32_t A6XX_CP_EVENT_END_STATE_ID(uint32_t val)
> +{
> + return ((val) << A6XX_CP_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_EVENT_END_STATE_ID__MASK;
> +}
> +
> +#define REG_A6XX_CP_2D_EVENT_START 0x0000d700
> +#define A6XX_CP_2D_EVENT_START_STATE_ID__MASK 0x000000ff
> +#define A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT 0
> +static inline uint32_t A6XX_CP_2D_EVENT_START_STATE_ID(uint32_t val)
> +{
> + return ((val) << A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_START_STATE_ID__MASK;
> +}
> +
> +#define REG_A6XX_CP_2D_EVENT_END 0x0000d701
> +#define A6XX_CP_2D_EVENT_END_STATE_ID__MASK 0x000000ff
> +#define A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT 0
> +static inline uint32_t A6XX_CP_2D_EVENT_END_STATE_ID(uint32_t val)
> +{
> + return ((val) << A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_END_STATE_ID__MASK;
> +}
> +
> #define REG_A6XX_TEX_SAMP_0 0x00000000
> #define A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
> #define A6XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
> @@ -5081,6 +6463,7 @@ static inline uint32_t A6XX_TEX_SAMP_0_LOD_BIAS(float val)
> }
>
> #define REG_A6XX_TEX_SAMP_1 0x00000001
> +#define A6XX_TEX_SAMP_1_UNK0 0x00000001
> #define A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
> #define A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
> static inline uint32_t A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
> @@ -5104,11 +6487,18 @@ static inline uint32_t A6XX_TEX_SAMP_1_MIN_LOD(float val)
> }
>
> #define REG_A6XX_TEX_SAMP_2 0x00000002
> -#define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xfffffff0
> -#define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 4
> +#define A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK 0x00000003
> +#define A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT 0
> +static inline uint32_t A6XX_TEX_SAMP_2_REDUCTION_MODE(enum a6xx_reduction_mode val)
> +{
> + return ((val) << A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT) & A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK;
> +}
> +#define A6XX_TEX_SAMP_2_CHROMA_LINEAR 0x00000020
> +#define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xffffff80
> +#define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 7
> static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)
> {
> - return ((val) << A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;
> + return ((val >> 7) << A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;
> }
>
> #define REG_A6XX_TEX_SAMP_3 0x00000003
> @@ -5151,6 +6541,8 @@ static inline uint32_t A6XX_TEX_CONST_0_MIPLVLS(uint32_t val)
> {
> return ((val) << A6XX_TEX_CONST_0_MIPLVLS__SHIFT) & A6XX_TEX_CONST_0_MIPLVLS__MASK;
> }
> +#define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X 0x00010000
> +#define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y 0x00040000
> #define A6XX_TEX_CONST_0_SAMPLES__MASK 0x00300000
> #define A6XX_TEX_CONST_0_SAMPLES__SHIFT 20
> static inline uint32_t A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val)
> @@ -5159,7 +6551,7 @@ static inline uint32_t A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val)
> }
> #define A6XX_TEX_CONST_0_FMT__MASK 0x3fc00000
> #define A6XX_TEX_CONST_0_FMT__SHIFT 22
> -static inline uint32_t A6XX_TEX_CONST_0_FMT(enum a6xx_tex_fmt val)
> +static inline uint32_t A6XX_TEX_CONST_0_FMT(enum a6xx_format val)
> {
> return ((val) << A6XX_TEX_CONST_0_FMT__SHIFT) & A6XX_TEX_CONST_0_FMT__MASK;
> }
> @@ -5185,11 +6577,12 @@ static inline uint32_t A6XX_TEX_CONST_1_HEIGHT(uint32_t val)
> }
>
> #define REG_A6XX_TEX_CONST_2 0x00000002
> -#define A6XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f
> -#define A6XX_TEX_CONST_2_FETCHSIZE__SHIFT 0
> -static inline uint32_t A6XX_TEX_CONST_2_FETCHSIZE(enum a6xx_tex_fetchsize val)
> +#define A6XX_TEX_CONST_2_UNK4 0x00000010
> +#define A6XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f
> +#define A6XX_TEX_CONST_2_PITCHALIGN__SHIFT 0
> +static inline uint32_t A6XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
> {
> - return ((val) << A6XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A6XX_TEX_CONST_2_FETCHSIZE__MASK;
> + return ((val) << A6XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A6XX_TEX_CONST_2_PITCHALIGN__MASK;
> }
> #define A6XX_TEX_CONST_2_PITCH__MASK 0x1fffff80
> #define A6XX_TEX_CONST_2_PITCH__SHIFT 7
> @@ -5203,6 +6596,7 @@ static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val)
> {
> return ((val) << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK;
> }
> +#define A6XX_TEX_CONST_2_UNK31 0x80000000
>
> #define REG_A6XX_TEX_CONST_3 0x00000003
> #define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff
> @@ -5211,6 +6605,13 @@ static inline uint32_t A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)
> {
> return ((val >> 12) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK;
> }
> +#define A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK 0x07800000
> +#define A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT 23
> +static inline uint32_t A6XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val)
> +{
> + return ((val >> 12) << A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK;
> +}
> +#define A6XX_TEX_CONST_3_TILE_ALL 0x08000000
> #define A6XX_TEX_CONST_3_FLAG 0x10000000
>
> #define REG_A6XX_TEX_CONST_4 0x00000004
> @@ -5236,6 +6637,12 @@ static inline uint32_t A6XX_TEX_CONST_5_DEPTH(uint32_t val)
> }
>
> #define REG_A6XX_TEX_CONST_6 0x00000006
> +#define A6XX_TEX_CONST_6_PLANE_PITCH__MASK 0xffffff00
> +#define A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT 8
> +static inline uint32_t A6XX_TEX_CONST_6_PLANE_PITCH(uint32_t val)
> +{
> + return ((val) << A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT) & A6XX_TEX_CONST_6_PLANE_PITCH__MASK;
> +}
>
> #define REG_A6XX_TEX_CONST_7 0x00000007
> #define A6XX_TEX_CONST_7_FLAG_LO__MASK 0xffffffe0
> @@ -5254,8 +6661,32 @@ static inline uint32_t A6XX_TEX_CONST_8_FLAG_HI(uint32_t val)
> }
>
> #define REG_A6XX_TEX_CONST_9 0x00000009
> +#define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK 0x0001ffff
> +#define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0
> +static inline uint32_t A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
> +{
> + return ((val >> 4) << A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK;
> +}
>
> #define REG_A6XX_TEX_CONST_10 0x0000000a
> +#define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK 0x0000007f
> +#define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT 0
> +static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(uint32_t val)
> +{
> + return ((val >> 6) << A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK;
> +}
> +#define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK 0x00000f00
> +#define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT 8
> +static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(uint32_t val)
> +{
> + return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK;
> +}
> +#define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK 0x0000f000
> +#define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT 12
> +static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(uint32_t val)
> +{
> + return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK;
> +}
>
> #define REG_A6XX_TEX_CONST_11 0x0000000b
>
> @@ -5267,6 +6698,126 @@ static inline uint32_t A6XX_TEX_CONST_8_FLAG_HI(uint32_t val)
>
> #define REG_A6XX_TEX_CONST_15 0x0000000f
>
> +#define REG_A6XX_IBO_0 0x00000000
> +#define A6XX_IBO_0_TILE_MODE__MASK 0x00000003
> +#define A6XX_IBO_0_TILE_MODE__SHIFT 0
> +static inline uint32_t A6XX_IBO_0_TILE_MODE(enum a6xx_tile_mode val)
> +{
> + return ((val) << A6XX_IBO_0_TILE_MODE__SHIFT) & A6XX_IBO_0_TILE_MODE__MASK;
> +}
> +#define A6XX_IBO_0_FMT__MASK 0x3fc00000
> +#define A6XX_IBO_0_FMT__SHIFT 22
> +static inline uint32_t A6XX_IBO_0_FMT(enum a6xx_format val)
> +{
> + return ((val) << A6XX_IBO_0_FMT__SHIFT) & A6XX_IBO_0_FMT__MASK;
> +}
> +
> +#define REG_A6XX_IBO_1 0x00000001
> +#define A6XX_IBO_1_WIDTH__MASK 0x00007fff
> +#define A6XX_IBO_1_WIDTH__SHIFT 0
> +static inline uint32_t A6XX_IBO_1_WIDTH(uint32_t val)
> +{
> + return ((val) << A6XX_IBO_1_WIDTH__SHIFT) & A6XX_IBO_1_WIDTH__MASK;
> +}
> +#define A6XX_IBO_1_HEIGHT__MASK 0x3fff8000
> +#define A6XX_IBO_1_HEIGHT__SHIFT 15
> +static inline uint32_t A6XX_IBO_1_HEIGHT(uint32_t val)
> +{
> + return ((val) << A6XX_IBO_1_HEIGHT__SHIFT) & A6XX_IBO_1_HEIGHT__MASK;
> +}
> +
> +#define REG_A6XX_IBO_2 0x00000002
> +#define A6XX_IBO_2_UNK4 0x00000010
> +#define A6XX_IBO_2_PITCH__MASK 0x1fffff80
> +#define A6XX_IBO_2_PITCH__SHIFT 7
> +static inline uint32_t A6XX_IBO_2_PITCH(uint32_t val)
> +{
> + return ((val) << A6XX_IBO_2_PITCH__SHIFT) & A6XX_IBO_2_PITCH__MASK;
> +}
> +#define A6XX_IBO_2_TYPE__MASK 0x60000000
> +#define A6XX_IBO_2_TYPE__SHIFT 29
> +static inline uint32_t A6XX_IBO_2_TYPE(enum a6xx_tex_type val)
> +{
> + return ((val) << A6XX_IBO_2_TYPE__SHIFT) & A6XX_IBO_2_TYPE__MASK;
> +}
> +#define A6XX_IBO_2_UNK31 0x80000000
> +
> +#define REG_A6XX_IBO_3 0x00000003
> +#define A6XX_IBO_3_ARRAY_PITCH__MASK 0x00003fff
> +#define A6XX_IBO_3_ARRAY_PITCH__SHIFT 0
> +static inline uint32_t A6XX_IBO_3_ARRAY_PITCH(uint32_t val)
> +{
> + return ((val >> 12) << A6XX_IBO_3_ARRAY_PITCH__SHIFT) & A6XX_IBO_3_ARRAY_PITCH__MASK;
> +}
> +#define A6XX_IBO_3_UNK27 0x08000000
> +#define A6XX_IBO_3_FLAG 0x10000000
> +
> +#define REG_A6XX_IBO_4 0x00000004
> +#define A6XX_IBO_4_BASE_LO__MASK 0xffffffff
> +#define A6XX_IBO_4_BASE_LO__SHIFT 0
> +static inline uint32_t A6XX_IBO_4_BASE_LO(uint32_t val)
> +{
> + return ((val) << A6XX_IBO_4_BASE_LO__SHIFT) & A6XX_IBO_4_BASE_LO__MASK;
> +}
> +
> +#define REG_A6XX_IBO_5 0x00000005
> +#define A6XX_IBO_5_BASE_HI__MASK 0x0001ffff
> +#define A6XX_IBO_5_BASE_HI__SHIFT 0
> +static inline uint32_t A6XX_IBO_5_BASE_HI(uint32_t val)
> +{
> + return ((val) << A6XX_IBO_5_BASE_HI__SHIFT) & A6XX_IBO_5_BASE_HI__MASK;
> +}
> +#define A6XX_IBO_5_DEPTH__MASK 0x3ffe0000
> +#define A6XX_IBO_5_DEPTH__SHIFT 17
> +static inline uint32_t A6XX_IBO_5_DEPTH(uint32_t val)
> +{
> + return ((val) << A6XX_IBO_5_DEPTH__SHIFT) & A6XX_IBO_5_DEPTH__MASK;
> +}
> +
> +#define REG_A6XX_IBO_6 0x00000006
> +
> +#define REG_A6XX_IBO_7 0x00000007
> +
> +#define REG_A6XX_IBO_8 0x00000008
> +
> +#define REG_A6XX_IBO_9 0x00000009
> +#define A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__MASK 0x0001ffff
> +#define A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0
> +static inline uint32_t A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
> +{
> + return ((val >> 4) << A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__MASK;
> +}
> +
> +#define REG_A6XX_IBO_10 0x0000000a
> +#define A6XX_IBO_10_FLAG_BUFFER_PITCH__MASK 0x0000007f
> +#define A6XX_IBO_10_FLAG_BUFFER_PITCH__SHIFT 0
> +static inline uint32_t A6XX_IBO_10_FLAG_BUFFER_PITCH(uint32_t val)
> +{
> + return ((val >> 6) << A6XX_IBO_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_IBO_10_FLAG_BUFFER_PITCH__MASK;
> +}
> +
> +#define REG_A6XX_UBO_0 0x00000000
> +#define A6XX_UBO_0_BASE_LO__MASK 0xffffffff
> +#define A6XX_UBO_0_BASE_LO__SHIFT 0
> +static inline uint32_t A6XX_UBO_0_BASE_LO(uint32_t val)
> +{
> + return ((val) << A6XX_UBO_0_BASE_LO__SHIFT) & A6XX_UBO_0_BASE_LO__MASK;
> +}
> +
> +#define REG_A6XX_UBO_1 0x00000001
> +#define A6XX_UBO_1_BASE_HI__MASK 0x0001ffff
> +#define A6XX_UBO_1_BASE_HI__SHIFT 0
> +static inline uint32_t A6XX_UBO_1_BASE_HI(uint32_t val)
> +{
> + return ((val) << A6XX_UBO_1_BASE_HI__SHIFT) & A6XX_UBO_1_BASE_HI__MASK;
> +}
> +#define A6XX_UBO_1_SIZE__MASK 0xfffe0000
> +#define A6XX_UBO_1_SIZE__SHIFT 17
> +static inline uint32_t A6XX_UBO_1_SIZE(uint32_t val)
> +{
> + return ((val) << A6XX_UBO_1_SIZE__SHIFT) & A6XX_UBO_1_SIZE__MASK;
> +}
> +
> #define REG_A6XX_PDC_GPU_ENABLE_PDC 0x00001140
>
> #define REG_A6XX_PDC_GPU_SEQ_START_ADDR 0x00001148
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
> index 176ae94d9fe6..86a89dce0c38 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
> @@ -8,19 +8,21 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
> git clone https://github.com/freedreno/envytools.git
>
> The rules-ng-ng source files this header was generated from are:
> -- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 42463 bytes, from 2018-11-19 13:44:03)
> -- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14201 bytes, from 2018-12-02 17:29:54)
> -- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43052 bytes, from 2018-12-02 17:29:54)
> -- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-02 17:29:54)
> -- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 140790 bytes, from 2018-12-02 17:29:54)
> -- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
> -- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
> -
> -Copyright (C) 2013-2018 by the following authors:
> +- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-06-21 22:29:16)
> +- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
> +- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 89649 bytes, from 2020-07-04 19:55:04)
> +- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14239 bytes, from 2020-07-04 19:55:04)
> +- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 63258 bytes, from 2020-07-07 19:26:50)
> +- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84246 bytes, from 2020-07-04 19:55:04)
> +- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112247 bytes, from 2020-07-04 19:55:04)
> +- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 148499 bytes, from 2020-07-04 20:00:49)
> +- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 174474 bytes, from 2020-07-04 20:56:59)
> +- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10768 bytes, from 2020-05-20 19:42:03)
> +- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
> +- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-06-21 22:29:16)
> +- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-06-21 22:29:43)
> +
> +Copyright (C) 2013-2020 by the following authors:
> - Rob Clark <robdclark@gmail.com> (robclark)
> - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_common.xml.h b/drivers/gpu/drm/msm/adreno/adreno_common.xml.h
> index 641d3ba477b6..e252326ae349 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_common.xml.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_common.xml.h
> @@ -8,19 +8,21 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
> git clone https://github.com/freedreno/envytools.git
>
> The rules-ng-ng source files this header was generated from are:
> -- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 42463 bytes, from 2018-11-19 13:44:03)
> -- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14201 bytes, from 2018-12-02 17:29:54)
> -- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43052 bytes, from 2018-12-02 17:29:54)
> -- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-02 17:29:54)
> -- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 140790 bytes, from 2018-12-02 17:29:54)
> -- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
> -- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
> -
> -Copyright (C) 2013-2018 by the following authors:
> +- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-06-21 22:29:16)
> +- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
> +- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 89649 bytes, from 2020-07-04 19:55:04)
> +- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14239 bytes, from 2020-07-04 19:55:04)
> +- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 63258 bytes, from 2020-07-07 19:26:50)
> +- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84246 bytes, from 2020-07-04 19:55:04)
> +- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112247 bytes, from 2020-07-04 19:55:04)
> +- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 148499 bytes, from 2020-07-04 20:00:49)
> +- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 174474 bytes, from 2020-07-04 20:56:59)
> +- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10768 bytes, from 2020-05-20 19:42:03)
> +- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
> +- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-06-21 22:29:16)
> +- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-06-21 22:29:43)
> +
> +Copyright (C) 2013-2020 by the following authors:
> - Rob Clark <robdclark@gmail.com> (robclark)
> - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
>
> @@ -159,6 +161,7 @@ enum a3xx_msaa_samples {
> MSAA_ONE = 0,
> MSAA_TWO = 1,
> MSAA_FOUR = 2,
> + MSAA_EIGHT = 3,
> };
>
> enum a3xx_threadmode {
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
> index 79b907ac0b4b..61613263b4e5 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
> @@ -8,19 +8,21 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
> git clone https://github.com/freedreno/envytools.git
>
> The rules-ng-ng source files this header was generated from are:
> -- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 42463 bytes, from 2018-11-19 13:44:03)
> -- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14201 bytes, from 2018-12-02 17:29:54)
> -- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43052 bytes, from 2018-12-02 17:29:54)
> -- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-02 17:29:54)
> -- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 140790 bytes, from 2018-12-02 17:29:54)
> -- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
> -- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
> -
> -Copyright (C) 2013-2018 by the following authors:
> +- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-06-21 22:29:16)
> +- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
> +- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 89649 bytes, from 2020-07-04 19:55:04)
> +- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14239 bytes, from 2020-07-04 19:55:04)
> +- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 63258 bytes, from 2020-07-07 19:26:50)
> +- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84246 bytes, from 2020-07-04 19:55:04)
> +- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112247 bytes, from 2020-07-04 19:55:04)
> +- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 148499 bytes, from 2020-07-04 20:00:49)
> +- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 174474 bytes, from 2020-07-04 20:56:59)
> +- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10768 bytes, from 2020-05-20 19:42:03)
> +- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
> +- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-06-21 22:29:16)
> +- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-06-21 22:29:43)
> +
> +Copyright (C) 2013-2020 by the following authors:
> - Rob Clark <robdclark@gmail.com> (robclark)
> - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
>
> @@ -54,10 +56,13 @@ enum vgt_event_type {
> CACHE_FLUSH_TS = 4,
> CONTEXT_DONE = 5,
> CACHE_FLUSH = 6,
> - HLSQ_FLUSH = 7,
> VIZQUERY_START = 7,
> + HLSQ_FLUSH = 7,
> VIZQUERY_END = 8,
> SC_WAIT_WC = 9,
> + WRITE_PRIMITIVE_COUNTS = 9,
> + START_PRIMITIVE_CTRS = 11,
> + STOP_PRIMITIVE_CTRS = 12,
> RST_PIX_CNT = 13,
> RST_VTX_CNT = 14,
> TILE_FLUSH = 15,
> @@ -65,23 +70,31 @@ enum vgt_event_type {
> CACHE_FLUSH_AND_INV_TS_EVENT = 20,
> ZPASS_DONE = 21,
> CACHE_FLUSH_AND_INV_EVENT = 22,
> + RB_DONE_TS = 22,
> PERFCOUNTER_START = 23,
> PERFCOUNTER_STOP = 24,
> VS_FETCH_DONE = 27,
> FACENESS_FLUSH = 28,
> + WT_DONE_TS = 8,
> FLUSH_SO_0 = 17,
> FLUSH_SO_1 = 18,
> FLUSH_SO_2 = 19,
> FLUSH_SO_3 = 20,
> PC_CCU_INVALIDATE_DEPTH = 24,
> PC_CCU_INVALIDATE_COLOR = 25,
> - UNK_1C = 28,
> - UNK_1D = 29,
> + PC_CCU_RESOLVE_TS = 26,
> + PC_CCU_FLUSH_DEPTH_TS = 28,
> + PC_CCU_FLUSH_COLOR_TS = 29,
> BLIT = 30,
> UNK_25 = 37,
> LRZ_FLUSH = 38,
> + BLIT_OP_FILL_2D = 39,
> + BLIT_OP_COPY_2D = 40,
> + BLIT_OP_SCALE_2D = 42,
> + CONTEXT_DONE_2D = 43,
> UNK_2C = 44,
> UNK_2D = 45,
> + CACHE_INVALIDATE = 49,
> };
>
> enum pc_di_primtype {
> @@ -99,13 +112,45 @@ enum pc_di_primtype {
> DI_PT_LINESTRIP_ADJ = 11,
> DI_PT_TRI_ADJ = 12,
> DI_PT_TRISTRIP_ADJ = 13,
> + DI_PT_PATCHES0 = 31,
> + DI_PT_PATCHES1 = 32,
> + DI_PT_PATCHES2 = 33,
> + DI_PT_PATCHES3 = 34,
> + DI_PT_PATCHES4 = 35,
> + DI_PT_PATCHES5 = 36,
> + DI_PT_PATCHES6 = 37,
> + DI_PT_PATCHES7 = 38,
> + DI_PT_PATCHES8 = 39,
> + DI_PT_PATCHES9 = 40,
> + DI_PT_PATCHES10 = 41,
> + DI_PT_PATCHES11 = 42,
> + DI_PT_PATCHES12 = 43,
> + DI_PT_PATCHES13 = 44,
> + DI_PT_PATCHES14 = 45,
> + DI_PT_PATCHES15 = 46,
> + DI_PT_PATCHES16 = 47,
> + DI_PT_PATCHES17 = 48,
> + DI_PT_PATCHES18 = 49,
> + DI_PT_PATCHES19 = 50,
> + DI_PT_PATCHES20 = 51,
> + DI_PT_PATCHES21 = 52,
> + DI_PT_PATCHES22 = 53,
> + DI_PT_PATCHES23 = 54,
> + DI_PT_PATCHES24 = 55,
> + DI_PT_PATCHES25 = 56,
> + DI_PT_PATCHES26 = 57,
> + DI_PT_PATCHES27 = 58,
> + DI_PT_PATCHES28 = 59,
> + DI_PT_PATCHES29 = 60,
> + DI_PT_PATCHES30 = 61,
> + DI_PT_PATCHES31 = 62,
> };
>
> enum pc_di_src_sel {
> DI_SRC_SEL_DMA = 0,
> DI_SRC_SEL_IMMEDIATE = 1,
> DI_SRC_SEL_AUTO_INDEX = 2,
> - DI_SRC_SEL_RESERVED = 3,
> + DI_SRC_SEL_AUTO_XFB = 3,
> };
>
> enum pc_di_face_cull_sel {
> @@ -143,6 +188,7 @@ enum adreno_pm4_type3_packets {
> CP_PREEMPT_ENABLE = 28,
> CP_PREEMPT_TOKEN = 30,
> CP_INDIRECT_BUFFER = 63,
> + CP_INDIRECT_BUFFER_CHAIN = 87,
> CP_INDIRECT_BUFFER_PFD = 55,
> CP_WAIT_FOR_IDLE = 38,
> CP_WAIT_REG_MEM = 60,
> @@ -199,6 +245,7 @@ enum adreno_pm4_type3_packets {
> CP_DRAW_INDX_OFFSET = 56,
> CP_DRAW_INDIRECT = 40,
> CP_DRAW_INDX_INDIRECT = 41,
> + CP_DRAW_INDIRECT_MULTI = 42,
> CP_DRAW_AUTO = 36,
> CP_UNKNOWN_19 = 25,
> CP_UNKNOWN_1A = 26,
> @@ -232,6 +279,7 @@ enum adreno_pm4_type3_packets {
> CP_SET_MODE = 99,
> CP_LOAD_STATE6_GEOM = 50,
> CP_LOAD_STATE6_FRAG = 52,
> + CP_LOAD_STATE6 = 54,
> IN_IB_PREFETCH_END = 23,
> IN_SUBBLK_PREFETCH = 31,
> IN_INSTR_PREFETCH = 32,
> @@ -241,9 +289,14 @@ enum adreno_pm4_type3_packets {
> IN_INCR_UPDT_CONST = 86,
> IN_INCR_UPDT_INSTR = 87,
> PKT4 = 4,
> - CP_UNK_A6XX_14 = 20,
> - CP_UNK_A6XX_36 = 54,
> - CP_UNK_A6XX_55 = 85,
> + CP_SCRATCH_WRITE = 76,
> + CP_REG_TO_MEM_OFFSET_MEM = 116,
> + CP_REG_TO_MEM_OFFSET_REG = 114,
> + CP_WAIT_MEM_GTE = 20,
> + CP_WAIT_TWO_REGS = 112,
> + CP_MEMCPY = 117,
> + CP_SET_BIN_DATA5_OFFSET = 46,
> + CP_SET_CTXSWITCH_IB = 85,
> CP_REG_WRITE = 109,
> };
>
> @@ -292,6 +345,7 @@ enum a4xx_state_block {
> enum a4xx_state_type {
> ST4_SHADER = 0,
> ST4_CONSTANTS = 1,
> + ST4_UBO = 2,
> };
>
> enum a4xx_state_src {
> @@ -312,17 +366,20 @@ enum a6xx_state_block {
> SB6_GS_SHADER = 11,
> SB6_FS_SHADER = 12,
> SB6_CS_SHADER = 13,
> - SB6_SSBO = 14,
> - SB6_CS_SSBO = 15,
> + SB6_IBO = 14,
> + SB6_CS_IBO = 15,
> };
>
> enum a6xx_state_type {
> ST6_SHADER = 0,
> ST6_CONSTANTS = 1,
> + ST6_UBO = 2,
> + ST6_IBO = 3,
> };
>
> enum a6xx_state_src {
> SS6_DIRECT = 0,
> + SS6_BINDLESS = 1,
> SS6_INDIRECT = 2,
> };
>
> @@ -332,6 +389,17 @@ enum a4xx_index_size {
> INDEX4_SIZE_32_BIT = 2,
> };
>
> +enum a6xx_patch_type {
> + TESS_QUADS = 0,
> + TESS_TRIANGLES = 1,
> + TESS_ISOLINES = 2,
> +};
> +
> +enum a6xx_draw_indirect_opcode {
> + INDIRECT_OP_NORMAL = 2,
> + INDIRECT_OP_INDEXED = 4,
> +};
> +
> enum cp_cond_function {
> WRITE_ALWAYS = 0,
> WRITE_LT = 1,
> @@ -361,9 +429,15 @@ enum a6xx_render_mode {
> RM6_BYPASS = 1,
> RM6_BINNING = 2,
> RM6_GMEM = 4,
> - RM6_BLIT2D = 5,
> + RM6_ENDVIS = 5,
> RM6_RESOLVE = 6,
> + RM6_YIELD = 7,
> + RM6_COMPUTE = 8,
> RM6_BLIT2DSCALE = 12,
> + RM6_IB1LIST_START = 13,
> + RM6_IB1LIST_END = 14,
> + RM6_IFPC_ENABLE = 256,
> + RM6_IFPC_DISABLE = 257,
> };
>
> enum pseudo_reg {
> @@ -374,6 +448,25 @@ enum pseudo_reg {
> COUNTER = 4,
> };
>
> +enum compare_mode {
> + PRED_TEST = 1,
> + REG_COMPARE = 2,
> + RENDER_MODE = 3,
> +};
> +
> +enum ctxswitch_ib {
> + RESTORE_IB = 0,
> + YIELD_RESTORE_IB = 1,
> + SAVE_IB = 2,
> + RB_SAVE_IB = 3,
> +};
> +
> +enum reg_tracker {
> + TRACK_CNTL_REG = 1,
> + TRACK_RENDER_CNTL = 2,
> + UNK_EVENT_WRITE = 4,
> +};
> +
> #define REG_CP_LOAD_STATE_0 0x00000000
> #define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff
> #define CP_LOAD_STATE_0_DST_OFF__SHIFT 0
> @@ -469,7 +562,7 @@ static inline uint32_t CP_LOAD_STATE6_0_DST_OFF(uint32_t val)
> {
> return ((val) << CP_LOAD_STATE6_0_DST_OFF__SHIFT) & CP_LOAD_STATE6_0_DST_OFF__MASK;
> }
> -#define CP_LOAD_STATE6_0_STATE_TYPE__MASK 0x00004000
> +#define CP_LOAD_STATE6_0_STATE_TYPE__MASK 0x0000c000
> #define CP_LOAD_STATE6_0_STATE_TYPE__SHIFT 14
> static inline uint32_t CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val)
> {
> @@ -510,6 +603,8 @@ static inline uint32_t CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(uint32_t val)
> return ((val) << CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK;
> }
>
> +#define REG_CP_LOAD_STATE6_EXT_SRC_ADDR 0x00000001
> +
> #define REG_CP_DRAW_INDX_0 0x00000000
> #define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff
> #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0
> @@ -653,12 +748,14 @@ static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val
> {
> return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
> }
> -#define CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK 0x01f00000
> -#define CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT 20
> -static inline uint32_t CP_DRAW_INDX_OFFSET_0_TESS_MODE(uint32_t val)
> +#define CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK 0x00003000
> +#define CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT 12
> +static inline uint32_t CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(enum a6xx_patch_type val)
> {
> - return ((val) << CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT) & CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK;
> + return ((val) << CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK;
> }
> +#define CP_DRAW_INDX_OFFSET_0_GS_ENABLE 0x00010000
> +#define CP_DRAW_INDX_OFFSET_0_TESS_ENABLE 0x00020000
>
> #define REG_CP_DRAW_INDX_OFFSET_1 0x00000001
> #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK 0xffffffff
> @@ -677,6 +774,39 @@ static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)
> }
>
> #define REG_CP_DRAW_INDX_OFFSET_3 0x00000003
> +#define CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK 0xffffffff
> +#define CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT 0
> +static inline uint32_t CP_DRAW_INDX_OFFSET_3_FIRST_INDX(uint32_t val)
> +{
> + return ((val) << CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT) & CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK;
> +}
> +
> +
> +#define REG_CP_DRAW_INDX_OFFSET_4 0x00000004
> +#define CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK 0xffffffff
> +#define CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT 0
> +static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO(uint32_t val)
> +{
> + return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK;
> +}
> +
> +#define REG_CP_DRAW_INDX_OFFSET_5 0x00000005
> +#define CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK 0xffffffff
> +#define CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT 0
> +static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI(uint32_t val)
> +{
> + return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK;
> +}
> +
> +#define REG_CP_DRAW_INDX_OFFSET_INDX_BASE 0x00000004
> +
> +#define REG_CP_DRAW_INDX_OFFSET_6 0x00000006
> +#define CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK 0xffffffff
> +#define CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT 0
> +static inline uint32_t CP_DRAW_INDX_OFFSET_6_MAX_INDICES(uint32_t val)
> +{
> + return ((val) << CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK;
> +}
>
> #define REG_CP_DRAW_INDX_OFFSET_4 0x00000004
> #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK 0xffffffff
> @@ -719,12 +849,15 @@ static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size v
> {
> return ((val) << A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK;
> }
> -#define A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__MASK 0x01f00000
> -#define A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT 20
> -static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_TESS_MODE(uint32_t val)
> +#define A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK 0x00003000
> +#define A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT 12
> +static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val)
> {
> - return ((val) << A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__MASK;
> + return ((val) << A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK;
> }
> +#define A4XX_CP_DRAW_INDIRECT_0_GS_ENABLE 0x00010000
> +#define A4XX_CP_DRAW_INDIRECT_0_TESS_ENABLE 0x00020000
> +
>
> #define REG_A4XX_CP_DRAW_INDIRECT_1 0x00000001
> #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK 0xffffffff
> @@ -735,6 +868,14 @@ static inline uint32_t A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val)
> }
>
>
> +#define REG_A5XX_CP_DRAW_INDIRECT_1 0x00000001
> +#define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK 0xffffffff
> +#define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT 0
> +static inline uint32_t A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO(uint32_t val)
> +{
> + return ((val) << A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK;
> +}
> +
> #define REG_A5XX_CP_DRAW_INDIRECT_2 0x00000002
> #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK 0xffffffff
> #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT 0
> @@ -743,6 +884,8 @@ static inline uint32_t A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val)
> return ((val) << A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK;
> }
>
> +#define REG_A5XX_CP_DRAW_INDIRECT_INDIRECT 0x00000001
> +
> #define REG_A4XX_CP_DRAW_INDX_INDIRECT_0 0x00000000
> #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f
> #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT 0
> @@ -768,12 +911,14 @@ static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_s
> {
> return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK;
> }
> -#define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__MASK 0x01f00000
> -#define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT 20
> -static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE(uint32_t val)
> +#define A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK 0x00003000
> +#define A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT 12
> +static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val)
> {
> - return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__MASK;
> + return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK;
> }
> +#define A4XX_CP_DRAW_INDX_INDIRECT_0_GS_ENABLE 0x00010000
> +#define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_ENABLE 0x00020000
>
>
> #define REG_A4XX_CP_DRAW_INDX_INDIRECT_1 0x00000001
> @@ -817,6 +962,8 @@ static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val)
> return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK;
> }
>
> +#define REG_A5XX_CP_DRAW_INDX_INDIRECT_INDX_BASE 0x00000001
> +
> #define REG_A5XX_CP_DRAW_INDX_INDIRECT_3 0x00000003
> #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK 0xffffffff
> #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT 0
> @@ -841,6 +988,84 @@ static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val)
> return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK;
> }
>
> +#define REG_A5XX_CP_DRAW_INDX_INDIRECT_INDIRECT 0x00000004
> +
> +#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_0 0x00000000
> +#define A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK 0x0000003f
> +#define A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT 0
> +static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE(enum pc_di_primtype val)
> +{
> + return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK;
> +}
> +#define A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK 0x000000c0
> +#define A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT 6
> +static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT(enum pc_di_src_sel val)
> +{
> + return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK;
> +}
> +#define A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK 0x00000300
> +#define A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT 8
> +static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL(enum pc_di_vis_cull_mode val)
> +{
> + return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK;
> +}
> +#define A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK 0x00000c00
> +#define A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT 10
> +static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE(enum a4xx_index_size val)
> +{
> + return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK;
> +}
> +#define A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK 0x00003000
> +#define A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT 12
> +static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE(enum a6xx_patch_type val)
> +{
> + return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK;
> +}
> +#define A6XX_CP_DRAW_INDIRECT_MULTI_0_GS_ENABLE 0x00010000
> +#define A6XX_CP_DRAW_INDIRECT_MULTI_0_TESS_ENABLE 0x00020000
> +
> +#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_1 0x00000001
> +#define A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK 0x0000000f
> +#define A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT 0
> +static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(enum a6xx_draw_indirect_opcode val)
> +{
> + return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK;
> +}
> +#define A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK 0x003fff00
> +#define A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT 8
> +static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(uint32_t val)
> +{
> + return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK;
> +}
> +
> +#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_2 0x00000002
> +#define A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__MASK 0xffffffff
> +#define A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__SHIFT 0
> +static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT(uint32_t val)
> +{
> + return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__MASK;
> +}
> +
> +#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_ADDRESS_0 0x00000003
> +
> +#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_5 0x00000005
> +#define A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__MASK 0xffffffff
> +#define A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__SHIFT 0
> +static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0(uint32_t val)
> +{
> + return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__MASK;
> +}
> +
> +#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000006
> +
> +#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_8 0x00000008
> +#define A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__MASK 0xffffffff
> +#define A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__SHIFT 0
> +static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE(uint32_t val)
> +{
> + return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__MASK;
> +}
> +
> static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
>
> static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
> @@ -854,12 +1079,9 @@ static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val)
> #define CP_SET_DRAW_STATE__0_DISABLE 0x00020000
> #define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS 0x00040000
> #define CP_SET_DRAW_STATE__0_LOAD_IMMED 0x00080000
> -#define CP_SET_DRAW_STATE__0_ENABLE_MASK__MASK 0x00f00000
> -#define CP_SET_DRAW_STATE__0_ENABLE_MASK__SHIFT 20
> -static inline uint32_t CP_SET_DRAW_STATE__0_ENABLE_MASK(uint32_t val)
> -{
> - return ((val) << CP_SET_DRAW_STATE__0_ENABLE_MASK__SHIFT) & CP_SET_DRAW_STATE__0_ENABLE_MASK__MASK;
> -}
> +#define CP_SET_DRAW_STATE__0_BINNING 0x00100000
> +#define CP_SET_DRAW_STATE__0_GMEM 0x00200000
> +#define CP_SET_DRAW_STATE__0_SYSMEM 0x00400000
> #define CP_SET_DRAW_STATE__0_GROUP_ID__MASK 0x1f000000
> #define CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT 24
> static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val)
> @@ -976,30 +1198,101 @@ static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)
> }
>
> #define REG_CP_SET_BIN_DATA5_5 0x00000005
> -#define CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__MASK 0xffffffff
> -#define CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__SHIFT 0
> -static inline uint32_t CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO(uint32_t val)
> +#define CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK 0xffffffff
> +#define CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT 0
> +static inline uint32_t CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO(uint32_t val)
> {
> - return ((val) << CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__SHIFT) & CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__MASK;
> + return ((val) << CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT) & CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK;
> }
>
> #define REG_CP_SET_BIN_DATA5_6 0x00000006
> -#define CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__MASK 0xffffffff
> -#define CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__SHIFT 0
> -static inline uint32_t CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO(uint32_t val)
> +#define CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK 0xffffffff
> +#define CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT 0
> +static inline uint32_t CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI(uint32_t val)
> +{
> + return ((val) << CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT) & CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK;
> +}
> +
> +#define REG_CP_SET_BIN_DATA5_OFFSET_0 0x00000000
> +#define CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK 0x003f0000
> +#define CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT 16
> +static inline uint32_t CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE(uint32_t val)
> +{
> + return ((val) << CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK;
> +}
> +#define CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK 0x07c00000
> +#define CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT 22
> +static inline uint32_t CP_SET_BIN_DATA5_OFFSET_0_VSC_N(uint32_t val)
> +{
> + return ((val) << CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK;
> +}
> +
> +#define REG_CP_SET_BIN_DATA5_OFFSET_1 0x00000001
> +#define CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK 0xffffffff
> +#define CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT 0
> +static inline uint32_t CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET(uint32_t val)
> +{
> + return ((val) << CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK;
> +}
> +
> +#define REG_CP_SET_BIN_DATA5_OFFSET_2 0x00000002
> +#define CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK 0xffffffff
> +#define CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT 0
> +static inline uint32_t CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET(uint32_t val)
> +{
> + return ((val) << CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK;
> +}
> +
> +#define REG_CP_SET_BIN_DATA5_OFFSET_3 0x00000003
> +#define CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK 0xffffffff
> +#define CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT 0
> +static inline uint32_t CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET(uint32_t val)
> +{
> + return ((val) << CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK;
> +}
> +
> +#define REG_CP_REG_RMW_0 0x00000000
> +#define CP_REG_RMW_0_DST_REG__MASK 0x0003ffff
> +#define CP_REG_RMW_0_DST_REG__SHIFT 0
> +static inline uint32_t CP_REG_RMW_0_DST_REG(uint32_t val)
> +{
> + return ((val) << CP_REG_RMW_0_DST_REG__SHIFT) & CP_REG_RMW_0_DST_REG__MASK;
> +}
> +#define CP_REG_RMW_0_ROTATE__MASK 0x1f000000
> +#define CP_REG_RMW_0_ROTATE__SHIFT 24
> +static inline uint32_t CP_REG_RMW_0_ROTATE(uint32_t val)
> +{
> + return ((val) << CP_REG_RMW_0_ROTATE__SHIFT) & CP_REG_RMW_0_ROTATE__MASK;
> +}
> +#define CP_REG_RMW_0_SRC1_ADD 0x20000000
> +#define CP_REG_RMW_0_SRC1_IS_REG 0x40000000
> +#define CP_REG_RMW_0_SRC0_IS_REG 0x80000000
> +
> +#define REG_CP_REG_RMW_1 0x00000001
> +#define CP_REG_RMW_1_SRC0__MASK 0xffffffff
> +#define CP_REG_RMW_1_SRC0__SHIFT 0
> +static inline uint32_t CP_REG_RMW_1_SRC0(uint32_t val)
> +{
> + return ((val) << CP_REG_RMW_1_SRC0__SHIFT) & CP_REG_RMW_1_SRC0__MASK;
> +}
> +
> +#define REG_CP_REG_RMW_2 0x00000002
> +#define CP_REG_RMW_2_SRC1__MASK 0xffffffff
> +#define CP_REG_RMW_2_SRC1__SHIFT 0
> +static inline uint32_t CP_REG_RMW_2_SRC1(uint32_t val)
> {
> - return ((val) << CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__SHIFT) & CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__MASK;
> + return ((val) << CP_REG_RMW_2_SRC1__SHIFT) & CP_REG_RMW_2_SRC1__MASK;
> }
>
> #define REG_CP_REG_TO_MEM_0 0x00000000
> -#define CP_REG_TO_MEM_0_REG__MASK 0x0000ffff
> +#define CP_REG_TO_MEM_0_REG__MASK 0x0003ffff
> #define CP_REG_TO_MEM_0_REG__SHIFT 0
> static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val)
> {
> return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK;
> }
> -#define CP_REG_TO_MEM_0_CNT__MASK 0x3ff80000
> -#define CP_REG_TO_MEM_0_CNT__SHIFT 19
> +#define CP_REG_TO_MEM_0_CNT__MASK 0x3ffc0000
> +#define CP_REG_TO_MEM_0_CNT__SHIFT 18
> static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val)
> {
> return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK;
> @@ -1023,8 +1316,97 @@ static inline uint32_t CP_REG_TO_MEM_2_DEST_HI(uint32_t val)
> return ((val) << CP_REG_TO_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_2_DEST_HI__MASK;
> }
>
> +#define REG_CP_REG_TO_MEM_OFFSET_REG_0 0x00000000
> +#define CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK 0x0003ffff
> +#define CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT 0
> +static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_0_REG(uint32_t val)
> +{
> + return ((val) << CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK;
> +}
> +#define CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK 0x3ffc0000
> +#define CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT 18
> +static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_0_CNT(uint32_t val)
> +{
> + return ((val) << CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK;
> +}
> +#define CP_REG_TO_MEM_OFFSET_REG_0_64B 0x40000000
> +#define CP_REG_TO_MEM_OFFSET_REG_0_ACCUMULATE 0x80000000
> +
> +#define REG_CP_REG_TO_MEM_OFFSET_REG_1 0x00000001
> +#define CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK 0xffffffff
> +#define CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT 0
> +static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_1_DEST(uint32_t val)
> +{
> + return ((val) << CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK;
> +}
> +
> +#define REG_CP_REG_TO_MEM_OFFSET_REG_2 0x00000002
> +#define CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK 0xffffffff
> +#define CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT 0
> +static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI(uint32_t val)
> +{
> + return ((val) << CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK;
> +}
> +
> +#define REG_CP_REG_TO_MEM_OFFSET_REG_3 0x00000003
> +#define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK 0x0003ffff
> +#define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT 0
> +static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0(uint32_t val)
> +{
> + return ((val) << CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK;
> +}
> +#define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0_SCRATCH 0x00080000
> +
> +#define REG_CP_REG_TO_MEM_OFFSET_MEM_0 0x00000000
> +#define CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK 0x0003ffff
> +#define CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT 0
> +static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_0_REG(uint32_t val)
> +{
> + return ((val) << CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK;
> +}
> +#define CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK 0x3ffc0000
> +#define CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT 18
> +static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_0_CNT(uint32_t val)
> +{
> + return ((val) << CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK;
> +}
> +#define CP_REG_TO_MEM_OFFSET_MEM_0_64B 0x40000000
> +#define CP_REG_TO_MEM_OFFSET_MEM_0_ACCUMULATE 0x80000000
> +
> +#define REG_CP_REG_TO_MEM_OFFSET_MEM_1 0x00000001
> +#define CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK 0xffffffff
> +#define CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT 0
> +static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_1_DEST(uint32_t val)
> +{
> + return ((val) << CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK;
> +}
> +
> +#define REG_CP_REG_TO_MEM_OFFSET_MEM_2 0x00000002
> +#define CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK 0xffffffff
> +#define CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT 0
> +static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI(uint32_t val)
> +{
> + return ((val) << CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK;
> +}
> +
> +#define REG_CP_REG_TO_MEM_OFFSET_MEM_3 0x00000003
> +#define CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK 0xffffffff
> +#define CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT 0
> +static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO(uint32_t val)
> +{
> + return ((val) << CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK;
> +}
> +
> +#define REG_CP_REG_TO_MEM_OFFSET_MEM_4 0x00000004
> +#define CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK 0xffffffff
> +#define CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT 0
> +static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI(uint32_t val)
> +{
> + return ((val) << CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK;
> +}
> +
> #define REG_CP_MEM_TO_REG_0 0x00000000
> -#define CP_MEM_TO_REG_0_REG__MASK 0x0000ffff
> +#define CP_MEM_TO_REG_0_REG__MASK 0x0003ffff
> #define CP_MEM_TO_REG_0_REG__SHIFT 0
> static inline uint32_t CP_MEM_TO_REG_0_REG(uint32_t val)
> {
> @@ -1036,8 +1418,8 @@ static inline uint32_t CP_MEM_TO_REG_0_CNT(uint32_t val)
> {
> return ((val) << CP_MEM_TO_REG_0_CNT__SHIFT) & CP_MEM_TO_REG_0_CNT__MASK;
> }
> -#define CP_MEM_TO_REG_0_64B 0x40000000
> -#define CP_MEM_TO_REG_0_ACCUMULATE 0x80000000
> +#define CP_MEM_TO_REG_0_SHIFT_BY_2 0x40000000
> +#define CP_MEM_TO_REG_0_UNK31 0x80000000
>
> #define REG_CP_MEM_TO_REG_1 0x00000001
> #define CP_MEM_TO_REG_1_SRC__MASK 0xffffffff
> @@ -1060,6 +1442,113 @@ static inline uint32_t CP_MEM_TO_REG_2_SRC_HI(uint32_t val)
> #define CP_MEM_TO_MEM_0_NEG_B 0x00000002
> #define CP_MEM_TO_MEM_0_NEG_C 0x00000004
> #define CP_MEM_TO_MEM_0_DOUBLE 0x20000000
> +#define CP_MEM_TO_MEM_0_WAIT_FOR_MEM_WRITES 0x40000000
> +#define CP_MEM_TO_MEM_0_UNK31 0x80000000
> +
> +#define REG_CP_MEMCPY_0 0x00000000
> +#define CP_MEMCPY_0_DWORDS__MASK 0xffffffff
> +#define CP_MEMCPY_0_DWORDS__SHIFT 0
> +static inline uint32_t CP_MEMCPY_0_DWORDS(uint32_t val)
> +{
> + return ((val) << CP_MEMCPY_0_DWORDS__SHIFT) & CP_MEMCPY_0_DWORDS__MASK;
> +}
> +
> +#define REG_CP_MEMCPY_1 0x00000001
> +#define CP_MEMCPY_1_SRC_LO__MASK 0xffffffff
> +#define CP_MEMCPY_1_SRC_LO__SHIFT 0
> +static inline uint32_t CP_MEMCPY_1_SRC_LO(uint32_t val)
> +{
> + return ((val) << CP_MEMCPY_1_SRC_LO__SHIFT) & CP_MEMCPY_1_SRC_LO__MASK;
> +}
> +
> +#define REG_CP_MEMCPY_2 0x00000002
> +#define CP_MEMCPY_2_SRC_HI__MASK 0xffffffff
> +#define CP_MEMCPY_2_SRC_HI__SHIFT 0
> +static inline uint32_t CP_MEMCPY_2_SRC_HI(uint32_t val)
> +{
> + return ((val) << CP_MEMCPY_2_SRC_HI__SHIFT) & CP_MEMCPY_2_SRC_HI__MASK;
> +}
> +
> +#define REG_CP_MEMCPY_3 0x00000003
> +#define CP_MEMCPY_3_DST_LO__MASK 0xffffffff
> +#define CP_MEMCPY_3_DST_LO__SHIFT 0
> +static inline uint32_t CP_MEMCPY_3_DST_LO(uint32_t val)
> +{
> + return ((val) << CP_MEMCPY_3_DST_LO__SHIFT) & CP_MEMCPY_3_DST_LO__MASK;
> +}
> +
> +#define REG_CP_MEMCPY_4 0x00000004
> +#define CP_MEMCPY_4_DST_HI__MASK 0xffffffff
> +#define CP_MEMCPY_4_DST_HI__SHIFT 0
> +static inline uint32_t CP_MEMCPY_4_DST_HI(uint32_t val)
> +{
> + return ((val) << CP_MEMCPY_4_DST_HI__SHIFT) & CP_MEMCPY_4_DST_HI__MASK;
> +}
> +
> +#define REG_CP_REG_TO_SCRATCH_0 0x00000000
> +#define CP_REG_TO_SCRATCH_0_REG__MASK 0x0003ffff
> +#define CP_REG_TO_SCRATCH_0_REG__SHIFT 0
> +static inline uint32_t CP_REG_TO_SCRATCH_0_REG(uint32_t val)
> +{
> + return ((val) << CP_REG_TO_SCRATCH_0_REG__SHIFT) & CP_REG_TO_SCRATCH_0_REG__MASK;
> +}
> +#define CP_REG_TO_SCRATCH_0_SCRATCH__MASK 0x00700000
> +#define CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT 20
> +static inline uint32_t CP_REG_TO_SCRATCH_0_SCRATCH(uint32_t val)
> +{
> + return ((val) << CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT) & CP_REG_TO_SCRATCH_0_SCRATCH__MASK;
> +}
> +#define CP_REG_TO_SCRATCH_0_CNT__MASK 0x07000000
> +#define CP_REG_TO_SCRATCH_0_CNT__SHIFT 24
> +static inline uint32_t CP_REG_TO_SCRATCH_0_CNT(uint32_t val)
> +{
> + return ((val) << CP_REG_TO_SCRATCH_0_CNT__SHIFT) & CP_REG_TO_SCRATCH_0_CNT__MASK;
> +}
> +
> +#define REG_CP_SCRATCH_TO_REG_0 0x00000000
> +#define CP_SCRATCH_TO_REG_0_REG__MASK 0x0003ffff
> +#define CP_SCRATCH_TO_REG_0_REG__SHIFT 0
> +static inline uint32_t CP_SCRATCH_TO_REG_0_REG(uint32_t val)
> +{
> + return ((val) << CP_SCRATCH_TO_REG_0_REG__SHIFT) & CP_SCRATCH_TO_REG_0_REG__MASK;
> +}
> +#define CP_SCRATCH_TO_REG_0_UNK18 0x00040000
> +#define CP_SCRATCH_TO_REG_0_SCRATCH__MASK 0x00700000
> +#define CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT 20
> +static inline uint32_t CP_SCRATCH_TO_REG_0_SCRATCH(uint32_t val)
> +{
> + return ((val) << CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT) & CP_SCRATCH_TO_REG_0_SCRATCH__MASK;
> +}
> +#define CP_SCRATCH_TO_REG_0_CNT__MASK 0x07000000
> +#define CP_SCRATCH_TO_REG_0_CNT__SHIFT 24
> +static inline uint32_t CP_SCRATCH_TO_REG_0_CNT(uint32_t val)
> +{
> + return ((val) << CP_SCRATCH_TO_REG_0_CNT__SHIFT) & CP_SCRATCH_TO_REG_0_CNT__MASK;
> +}
> +
> +#define REG_CP_SCRATCH_WRITE_0 0x00000000
> +#define CP_SCRATCH_WRITE_0_SCRATCH__MASK 0x00700000
> +#define CP_SCRATCH_WRITE_0_SCRATCH__SHIFT 20
> +static inline uint32_t CP_SCRATCH_WRITE_0_SCRATCH(uint32_t val)
> +{
> + return ((val) << CP_SCRATCH_WRITE_0_SCRATCH__SHIFT) & CP_SCRATCH_WRITE_0_SCRATCH__MASK;
> +}
> +
> +#define REG_CP_MEM_WRITE_0 0x00000000
> +#define CP_MEM_WRITE_0_ADDR_LO__MASK 0xffffffff
> +#define CP_MEM_WRITE_0_ADDR_LO__SHIFT 0
> +static inline uint32_t CP_MEM_WRITE_0_ADDR_LO(uint32_t val)
> +{
> + return ((val) << CP_MEM_WRITE_0_ADDR_LO__SHIFT) & CP_MEM_WRITE_0_ADDR_LO__MASK;
> +}
> +
> +#define REG_CP_MEM_WRITE_1 0x00000001
> +#define CP_MEM_WRITE_1_ADDR_HI__MASK 0xffffffff
> +#define CP_MEM_WRITE_1_ADDR_HI__SHIFT 0
> +static inline uint32_t CP_MEM_WRITE_1_ADDR_HI(uint32_t val)
> +{
> + return ((val) << CP_MEM_WRITE_1_ADDR_HI__SHIFT) & CP_MEM_WRITE_1_ADDR_HI__MASK;
> +}
>
> #define REG_CP_COND_WRITE_0 0x00000000
> #define CP_COND_WRITE_0_FUNCTION__MASK 0x00000007
> @@ -1118,7 +1607,9 @@ static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val)
> {
> return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK;
> }
> +#define CP_COND_WRITE5_0_SIGNED_COMPARE 0x00000008
> #define CP_COND_WRITE5_0_POLL_MEMORY 0x00000010
> +#define CP_COND_WRITE5_0_POLL_SCRATCH 0x00000020
> #define CP_COND_WRITE5_0_WRITE_MEMORY 0x00000100
>
> #define REG_CP_COND_WRITE5_1 0x00000001
> @@ -1177,6 +1668,114 @@ static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val)
> return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK;
> }
>
> +#define REG_CP_WAIT_MEM_GTE_0 0x00000000
> +#define CP_WAIT_MEM_GTE_0_RESERVED__MASK 0xffffffff
> +#define CP_WAIT_MEM_GTE_0_RESERVED__SHIFT 0
> +static inline uint32_t CP_WAIT_MEM_GTE_0_RESERVED(uint32_t val)
> +{
> + return ((val) << CP_WAIT_MEM_GTE_0_RESERVED__SHIFT) & CP_WAIT_MEM_GTE_0_RESERVED__MASK;
> +}
> +
> +#define REG_CP_WAIT_MEM_GTE_1 0x00000001
> +#define CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK 0xffffffff
> +#define CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT 0
> +static inline uint32_t CP_WAIT_MEM_GTE_1_POLL_ADDR_LO(uint32_t val)
> +{
> + return ((val) << CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK;
> +}
> +
> +#define REG_CP_WAIT_MEM_GTE_2 0x00000002
> +#define CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK 0xffffffff
> +#define CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT 0
> +static inline uint32_t CP_WAIT_MEM_GTE_2_POLL_ADDR_HI(uint32_t val)
> +{
> + return ((val) << CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK;
> +}
> +
> +#define REG_CP_WAIT_MEM_GTE_3 0x00000003
> +#define CP_WAIT_MEM_GTE_3_REF__MASK 0xffffffff
> +#define CP_WAIT_MEM_GTE_3_REF__SHIFT 0
> +static inline uint32_t CP_WAIT_MEM_GTE_3_REF(uint32_t val)
> +{
> + return ((val) << CP_WAIT_MEM_GTE_3_REF__SHIFT) & CP_WAIT_MEM_GTE_3_REF__MASK;
> +}
> +
> +#define REG_CP_WAIT_REG_MEM_0 0x00000000
> +#define CP_WAIT_REG_MEM_0_FUNCTION__MASK 0x00000007
> +#define CP_WAIT_REG_MEM_0_FUNCTION__SHIFT 0
> +static inline uint32_t CP_WAIT_REG_MEM_0_FUNCTION(enum cp_cond_function val)
> +{
> + return ((val) << CP_WAIT_REG_MEM_0_FUNCTION__SHIFT) & CP_WAIT_REG_MEM_0_FUNCTION__MASK;
> +}
> +#define CP_WAIT_REG_MEM_0_SIGNED_COMPARE 0x00000008
> +#define CP_WAIT_REG_MEM_0_POLL_MEMORY 0x00000010
> +#define CP_WAIT_REG_MEM_0_POLL_SCRATCH 0x00000020
> +#define CP_WAIT_REG_MEM_0_WRITE_MEMORY 0x00000100
> +
> +#define REG_CP_WAIT_REG_MEM_1 0x00000001
> +#define CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK 0xffffffff
> +#define CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT 0
> +static inline uint32_t CP_WAIT_REG_MEM_1_POLL_ADDR_LO(uint32_t val)
> +{
> + return ((val) << CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK;
> +}
> +
> +#define REG_CP_WAIT_REG_MEM_2 0x00000002
> +#define CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK 0xffffffff
> +#define CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT 0
> +static inline uint32_t CP_WAIT_REG_MEM_2_POLL_ADDR_HI(uint32_t val)
> +{
> + return ((val) << CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK;
> +}
> +
> +#define REG_CP_WAIT_REG_MEM_3 0x00000003
> +#define CP_WAIT_REG_MEM_3_REF__MASK 0xffffffff
> +#define CP_WAIT_REG_MEM_3_REF__SHIFT 0
> +static inline uint32_t CP_WAIT_REG_MEM_3_REF(uint32_t val)
> +{
> + return ((val) << CP_WAIT_REG_MEM_3_REF__SHIFT) & CP_WAIT_REG_MEM_3_REF__MASK;
> +}
> +
> +#define REG_CP_WAIT_REG_MEM_4 0x00000004
> +#define CP_WAIT_REG_MEM_4_MASK__MASK 0xffffffff
> +#define CP_WAIT_REG_MEM_4_MASK__SHIFT 0
> +static inline uint32_t CP_WAIT_REG_MEM_4_MASK(uint32_t val)
> +{
> + return ((val) << CP_WAIT_REG_MEM_4_MASK__SHIFT) & CP_WAIT_REG_MEM_4_MASK__MASK;
> +}
> +
> +#define REG_CP_WAIT_REG_MEM_5 0x00000005
> +#define CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK 0xffffffff
> +#define CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT 0
> +static inline uint32_t CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(uint32_t val)
> +{
> + return ((val) << CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT) & CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK;
> +}
> +
> +#define REG_CP_WAIT_TWO_REGS_0 0x00000000
> +#define CP_WAIT_TWO_REGS_0_REG0__MASK 0x0003ffff
> +#define CP_WAIT_TWO_REGS_0_REG0__SHIFT 0
> +static inline uint32_t CP_WAIT_TWO_REGS_0_REG0(uint32_t val)
> +{
> + return ((val) << CP_WAIT_TWO_REGS_0_REG0__SHIFT) & CP_WAIT_TWO_REGS_0_REG0__MASK;
> +}
> +
> +#define REG_CP_WAIT_TWO_REGS_1 0x00000001
> +#define CP_WAIT_TWO_REGS_1_REG1__MASK 0x0003ffff
> +#define CP_WAIT_TWO_REGS_1_REG1__SHIFT 0
> +static inline uint32_t CP_WAIT_TWO_REGS_1_REG1(uint32_t val)
> +{
> + return ((val) << CP_WAIT_TWO_REGS_1_REG1__SHIFT) & CP_WAIT_TWO_REGS_1_REG1__MASK;
> +}
> +
> +#define REG_CP_WAIT_TWO_REGS_2 0x00000002
> +#define CP_WAIT_TWO_REGS_2_REF__MASK 0xffffffff
> +#define CP_WAIT_TWO_REGS_2_REF__SHIFT 0
> +static inline uint32_t CP_WAIT_TWO_REGS_2_REF(uint32_t val)
> +{
> + return ((val) << CP_WAIT_TWO_REGS_2_REF__SHIFT) & CP_WAIT_TWO_REGS_2_REF__MASK;
> +}
> +
> #define REG_CP_DISPATCH_COMPUTE_0 0x00000000
>
> #define REG_CP_DISPATCH_COMPUTE_1 0x00000001
> @@ -1329,6 +1928,7 @@ static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)
> return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK;
> }
> #define CP_EVENT_WRITE_0_TIMESTAMP 0x40000000
> +#define CP_EVENT_WRITE_0_IRQ 0x80000000
>
> #define REG_CP_EVENT_WRITE_1 0x00000001
> #define CP_EVENT_WRITE_1_ADDR_0_LO__MASK 0xffffffff
> @@ -1506,61 +2106,209 @@ static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val)
> return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK;
> }
>
> -#define REG_A2XX_CP_SET_MARKER_0 0x00000000
> -#define A2XX_CP_SET_MARKER_0_MARKER__MASK 0x0000000f
> -#define A2XX_CP_SET_MARKER_0_MARKER__SHIFT 0
> -static inline uint32_t A2XX_CP_SET_MARKER_0_MARKER(uint32_t val)
> +#define REG_A6XX_CP_SET_MARKER_0 0x00000000
> +#define A6XX_CP_SET_MARKER_0_MODE__MASK 0x000001ff
> +#define A6XX_CP_SET_MARKER_0_MODE__SHIFT 0
> +static inline uint32_t A6XX_CP_SET_MARKER_0_MODE(enum a6xx_render_mode val)
> +{
> + return ((val) << A6XX_CP_SET_MARKER_0_MODE__SHIFT) & A6XX_CP_SET_MARKER_0_MODE__MASK;
> +}
> +#define A6XX_CP_SET_MARKER_0_MARKER__MASK 0x0000000f
> +#define A6XX_CP_SET_MARKER_0_MARKER__SHIFT 0
> +static inline uint32_t A6XX_CP_SET_MARKER_0_MARKER(enum a6xx_render_mode val)
> +{
> + return ((val) << A6XX_CP_SET_MARKER_0_MARKER__SHIFT) & A6XX_CP_SET_MARKER_0_MARKER__MASK;
> +}
> +
> +static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
> +
> +static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
> +#define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK 0x00000007
> +#define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT 0
> +static inline uint32_t A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val)
> +{
> + return ((val) << A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT) & A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK;
> +}
> +
> +static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
> +#define A6XX_CP_SET_PSEUDO_REG__1_LO__MASK 0xffffffff
> +#define A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT 0
> +static inline uint32_t A6XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val)
> +{
> + return ((val) << A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT) & A6XX_CP_SET_PSEUDO_REG__1_LO__MASK;
> +}
> +
> +static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
> +#define A6XX_CP_SET_PSEUDO_REG__2_HI__MASK 0xffffffff
> +#define A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT 0
> +static inline uint32_t A6XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val)
> +{
> + return ((val) << A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT) & A6XX_CP_SET_PSEUDO_REG__2_HI__MASK;
> +}
> +
> +#define REG_A6XX_CP_REG_TEST_0 0x00000000
> +#define A6XX_CP_REG_TEST_0_REG__MASK 0x0003ffff
> +#define A6XX_CP_REG_TEST_0_REG__SHIFT 0
> +static inline uint32_t A6XX_CP_REG_TEST_0_REG(uint32_t val)
> +{
> + return ((val) << A6XX_CP_REG_TEST_0_REG__SHIFT) & A6XX_CP_REG_TEST_0_REG__MASK;
> +}
> +#define A6XX_CP_REG_TEST_0_BIT__MASK 0x01f00000
> +#define A6XX_CP_REG_TEST_0_BIT__SHIFT 20
> +static inline uint32_t A6XX_CP_REG_TEST_0_BIT(uint32_t val)
> +{
> + return ((val) << A6XX_CP_REG_TEST_0_BIT__SHIFT) & A6XX_CP_REG_TEST_0_BIT__MASK;
> +}
> +#define A6XX_CP_REG_TEST_0_WAIT_FOR_ME 0x02000000
> +
> +#define REG_CP_COND_REG_EXEC_0 0x00000000
> +#define CP_COND_REG_EXEC_0_REG0__MASK 0x0003ffff
> +#define CP_COND_REG_EXEC_0_REG0__SHIFT 0
> +static inline uint32_t CP_COND_REG_EXEC_0_REG0(uint32_t val)
> +{
> + return ((val) << CP_COND_REG_EXEC_0_REG0__SHIFT) & CP_COND_REG_EXEC_0_REG0__MASK;
> +}
> +#define CP_COND_REG_EXEC_0_BINNING 0x02000000
> +#define CP_COND_REG_EXEC_0_GMEM 0x04000000
> +#define CP_COND_REG_EXEC_0_SYSMEM 0x08000000
> +#define CP_COND_REG_EXEC_0_MODE__MASK 0xf0000000
> +#define CP_COND_REG_EXEC_0_MODE__SHIFT 28
> +static inline uint32_t CP_COND_REG_EXEC_0_MODE(enum compare_mode val)
> +{
> + return ((val) << CP_COND_REG_EXEC_0_MODE__SHIFT) & CP_COND_REG_EXEC_0_MODE__MASK;
> +}
> +
> +#define REG_CP_COND_REG_EXEC_1 0x00000001
> +#define CP_COND_REG_EXEC_1_DWORDS__MASK 0xffffffff
> +#define CP_COND_REG_EXEC_1_DWORDS__SHIFT 0
> +static inline uint32_t CP_COND_REG_EXEC_1_DWORDS(uint32_t val)
> +{
> + return ((val) << CP_COND_REG_EXEC_1_DWORDS__SHIFT) & CP_COND_REG_EXEC_1_DWORDS__MASK;
> +}
> +
> +#define REG_CP_COND_EXEC_0 0x00000000
> +#define CP_COND_EXEC_0_ADDR0_LO__MASK 0xffffffff
> +#define CP_COND_EXEC_0_ADDR0_LO__SHIFT 0
> +static inline uint32_t CP_COND_EXEC_0_ADDR0_LO(uint32_t val)
> +{
> + return ((val) << CP_COND_EXEC_0_ADDR0_LO__SHIFT) & CP_COND_EXEC_0_ADDR0_LO__MASK;
> +}
> +
> +#define REG_CP_COND_EXEC_1 0x00000001
> +#define CP_COND_EXEC_1_ADDR0_HI__MASK 0xffffffff
> +#define CP_COND_EXEC_1_ADDR0_HI__SHIFT 0
> +static inline uint32_t CP_COND_EXEC_1_ADDR0_HI(uint32_t val)
> {
> - return ((val) << A2XX_CP_SET_MARKER_0_MARKER__SHIFT) & A2XX_CP_SET_MARKER_0_MARKER__MASK;
> + return ((val) << CP_COND_EXEC_1_ADDR0_HI__SHIFT) & CP_COND_EXEC_1_ADDR0_HI__MASK;
> }
> -#define A2XX_CP_SET_MARKER_0_MODE__MASK 0x0000000f
> -#define A2XX_CP_SET_MARKER_0_MODE__SHIFT 0
> -static inline uint32_t A2XX_CP_SET_MARKER_0_MODE(enum a6xx_render_mode val)
> +
> +#define REG_CP_COND_EXEC_2 0x00000002
> +#define CP_COND_EXEC_2_ADDR1_LO__MASK 0xffffffff
> +#define CP_COND_EXEC_2_ADDR1_LO__SHIFT 0
> +static inline uint32_t CP_COND_EXEC_2_ADDR1_LO(uint32_t val)
> +{
> + return ((val) << CP_COND_EXEC_2_ADDR1_LO__SHIFT) & CP_COND_EXEC_2_ADDR1_LO__MASK;
> +}
> +
> +#define REG_CP_COND_EXEC_3 0x00000003
> +#define CP_COND_EXEC_3_ADDR1_HI__MASK 0xffffffff
> +#define CP_COND_EXEC_3_ADDR1_HI__SHIFT 0
> +static inline uint32_t CP_COND_EXEC_3_ADDR1_HI(uint32_t val)
> {
> - return ((val) << A2XX_CP_SET_MARKER_0_MODE__SHIFT) & A2XX_CP_SET_MARKER_0_MODE__MASK;
> + return ((val) << CP_COND_EXEC_3_ADDR1_HI__SHIFT) & CP_COND_EXEC_3_ADDR1_HI__MASK;
> }
> -#define A2XX_CP_SET_MARKER_0_IFPC 0x00000100
>
> -static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
> +#define REG_CP_COND_EXEC_4 0x00000004
> +#define CP_COND_EXEC_4_REF__MASK 0xffffffff
> +#define CP_COND_EXEC_4_REF__SHIFT 0
> +static inline uint32_t CP_COND_EXEC_4_REF(uint32_t val)
> +{
> + return ((val) << CP_COND_EXEC_4_REF__SHIFT) & CP_COND_EXEC_4_REF__MASK;
> +}
>
> -static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
> -#define A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK 0x00000007
> -#define A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT 0
> -static inline uint32_t A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val)
> +#define REG_CP_COND_EXEC_5 0x00000005
> +#define CP_COND_EXEC_5_DWORDS__MASK 0xffffffff
> +#define CP_COND_EXEC_5_DWORDS__SHIFT 0
> +static inline uint32_t CP_COND_EXEC_5_DWORDS(uint32_t val)
> {
> - return ((val) << A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT) & A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK;
> + return ((val) << CP_COND_EXEC_5_DWORDS__SHIFT) & CP_COND_EXEC_5_DWORDS__MASK;
> }
>
> -static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
> -#define A2XX_CP_SET_PSEUDO_REG__1_LO__MASK 0xffffffff
> -#define A2XX_CP_SET_PSEUDO_REG__1_LO__SHIFT 0
> -static inline uint32_t A2XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val)
> +#define REG_CP_SET_CTXSWITCH_IB_0 0x00000000
> +#define CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK 0xffffffff
> +#define CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT 0
> +static inline uint32_t CP_SET_CTXSWITCH_IB_0_ADDR_LO(uint32_t val)
> {
> - return ((val) << A2XX_CP_SET_PSEUDO_REG__1_LO__SHIFT) & A2XX_CP_SET_PSEUDO_REG__1_LO__MASK;
> + return ((val) << CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT) & CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK;
> }
>
> -static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
> -#define A2XX_CP_SET_PSEUDO_REG__2_HI__MASK 0xffffffff
> -#define A2XX_CP_SET_PSEUDO_REG__2_HI__SHIFT 0
> -static inline uint32_t A2XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val)
> +#define REG_CP_SET_CTXSWITCH_IB_1 0x00000001
> +#define CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK 0xffffffff
> +#define CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT 0
> +static inline uint32_t CP_SET_CTXSWITCH_IB_1_ADDR_HI(uint32_t val)
> {
> - return ((val) << A2XX_CP_SET_PSEUDO_REG__2_HI__SHIFT) & A2XX_CP_SET_PSEUDO_REG__2_HI__MASK;
> + return ((val) << CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT) & CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK;
> }
>
> -#define REG_A2XX_CP_REG_TEST_0 0x00000000
> -#define A2XX_CP_REG_TEST_0_REG__MASK 0x00000fff
> -#define A2XX_CP_REG_TEST_0_REG__SHIFT 0
> -static inline uint32_t A2XX_CP_REG_TEST_0_REG(uint32_t val)
> +#define REG_CP_SET_CTXSWITCH_IB_2 0x00000002
> +#define CP_SET_CTXSWITCH_IB_2_DWORDS__MASK 0x000fffff
> +#define CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT 0
> +static inline uint32_t CP_SET_CTXSWITCH_IB_2_DWORDS(uint32_t val)
> +{
> + return ((val) << CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT) & CP_SET_CTXSWITCH_IB_2_DWORDS__MASK;
> +}
> +#define CP_SET_CTXSWITCH_IB_2_TYPE__MASK 0x00300000
> +#define CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT 20
> +static inline uint32_t CP_SET_CTXSWITCH_IB_2_TYPE(enum ctxswitch_ib val)
> {
> - return ((val) << A2XX_CP_REG_TEST_0_REG__SHIFT) & A2XX_CP_REG_TEST_0_REG__MASK;
> + return ((val) << CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT) & CP_SET_CTXSWITCH_IB_2_TYPE__MASK;
> }
> -#define A2XX_CP_REG_TEST_0_BIT__MASK 0x01f00000
> -#define A2XX_CP_REG_TEST_0_BIT__SHIFT 20
> -static inline uint32_t A2XX_CP_REG_TEST_0_BIT(uint32_t val)
> +
> +#define REG_CP_REG_WRITE_0 0x00000000
> +#define CP_REG_WRITE_0_TRACKER__MASK 0x00000007
> +#define CP_REG_WRITE_0_TRACKER__SHIFT 0
> +static inline uint32_t CP_REG_WRITE_0_TRACKER(enum reg_tracker val)
> +{
> + return ((val) << CP_REG_WRITE_0_TRACKER__SHIFT) & CP_REG_WRITE_0_TRACKER__MASK;
> +}
> +
> +#define REG_CP_SMMU_TABLE_UPDATE_0 0x00000000
> +#define CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK 0xffffffff
> +#define CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT 0
> +static inline uint32_t CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(uint32_t val)
> +{
> + return ((val) << CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT) & CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK;
> +}
> +
> +#define REG_CP_SMMU_TABLE_UPDATE_1 0x00000001
> +#define CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK 0x0000ffff
> +#define CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT 0
> +static inline uint32_t CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(uint32_t val)
> +{
> + return ((val) << CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT) & CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK;
> +}
> +#define CP_SMMU_TABLE_UPDATE_1_ASID__MASK 0xffff0000
> +#define CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT 16
> +static inline uint32_t CP_SMMU_TABLE_UPDATE_1_ASID(uint32_t val)
> +{
> + return ((val) << CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT) & CP_SMMU_TABLE_UPDATE_1_ASID__MASK;
> +}
> +
> +#define REG_CP_SMMU_TABLE_UPDATE_2 0x00000002
> +#define CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK 0xffffffff
> +#define CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT 0
> +static inline uint32_t CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(uint32_t val)
> +{
> + return ((val) << CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT) & CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK;
> +}
> +
> +#define REG_CP_SMMU_TABLE_UPDATE_3 0x00000003
> +#define CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK 0xffffffff
> +#define CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT 0
> +static inline uint32_t CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(uint32_t val)
> {
> - return ((val) << A2XX_CP_REG_TEST_0_BIT__SHIFT) & A2XX_CP_REG_TEST_0_BIT__MASK;
> + return ((val) << CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT) & CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK;
> }
> -#define A2XX_CP_REG_TEST_0_UNK25 0x02000000
>
>
> #endif /* ADRENO_PM4_XML */
> diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h b/drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h
> index 4b36b8954bae..1e37ba66312e 100644
> --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h
> +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h
> @@ -13,7 +13,7 @@ The rules-ng-ng source files this header was generated from are:
> - /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-07-03 19:37:13)
> +- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-04 21:03:00)
> - /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2018-07-03 19:37:13)
> diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h b/drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h
> index 784d98989e3a..88530b46cfbd 100644
> --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h
> +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h
> @@ -13,7 +13,7 @@ The rules-ng-ng source files this header was generated from are:
> - /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-07-03 19:37:13)
> +- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-04 21:03:00)
> - /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2018-07-03 19:37:13)
> diff --git a/drivers/gpu/drm/msm/disp/mdp_common.xml.h b/drivers/gpu/drm/msm/disp/mdp_common.xml.h
> index d420c8044e23..d29aceb3e843 100644
> --- a/drivers/gpu/drm/msm/disp/mdp_common.xml.h
> +++ b/drivers/gpu/drm/msm/disp/mdp_common.xml.h
> @@ -13,7 +13,7 @@ The rules-ng-ng source files this header was generated from are:
> - /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-07-03 19:37:13)
> +- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-04 21:03:00)
> - /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2018-07-03 19:37:13)
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h
> index 21f489a737d7..aaf42ba54c9b 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h
> @@ -13,14 +13,14 @@ The rules-ng-ng source files this header was generated from are:
> - /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-07-03 19:37:13)
> +- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-04 21:03:00)
> - /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2018-07-03 19:37:13)
>
> -Copyright (C) 2013-2018 by the following authors:
> +Copyright (C) 2013-2020 by the following authors:
> - Rob Clark <robdclark@gmail.com> (robclark)
> - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
>
> @@ -148,7 +148,31 @@ static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val)
> #define DSI_STATUS0_INTERLEAVE_OP_CONTENTION 0x80000000
>
> #define REG_DSI_FIFO_STATUS 0x00000008
> +#define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_OVERFLOW 0x00000001
> +#define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_UNDERFLOW 0x00000008
> #define DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW 0x00000080
> +#define DSI_FIFO_STATUS_CMD_DMA_FIFO_RD_WATERMARK_REACH 0x00000100
> +#define DSI_FIFO_STATUS_CMD_DMA_FIFO_WR_WATERMARK_REACH 0x00000200
> +#define DSI_FIFO_STATUS_CMD_DMA_FIFO_UNDERFLOW 0x00000400
> +#define DSI_FIFO_STATUS_DLN0_LP_FIFO_EMPTY 0x00001000
> +#define DSI_FIFO_STATUS_DLN0_LP_FIFO_FULL 0x00002000
> +#define DSI_FIFO_STATUS_DLN0_LP_FIFO_OVERFLOW 0x00004000
> +#define DSI_FIFO_STATUS_DLN0_HS_FIFO_EMPTY 0x00010000
> +#define DSI_FIFO_STATUS_DLN0_HS_FIFO_FULL 0x00020000
> +#define DSI_FIFO_STATUS_DLN0_HS_FIFO_OVERFLOW 0x00040000
> +#define DSI_FIFO_STATUS_DLN0_HS_FIFO_UNDERFLOW 0x00080000
> +#define DSI_FIFO_STATUS_DLN1_HS_FIFO_EMPTY 0x00100000
> +#define DSI_FIFO_STATUS_DLN1_HS_FIFO_FULL 0x00200000
> +#define DSI_FIFO_STATUS_DLN1_HS_FIFO_OVERFLOW 0x00400000
> +#define DSI_FIFO_STATUS_DLN1_HS_FIFO_UNDERFLOW 0x00800000
> +#define DSI_FIFO_STATUS_DLN2_HS_FIFO_EMPTY 0x01000000
> +#define DSI_FIFO_STATUS_DLN2_HS_FIFO_FULL 0x02000000
> +#define DSI_FIFO_STATUS_DLN2_HS_FIFO_OVERFLOW 0x04000000
> +#define DSI_FIFO_STATUS_DLN2_HS_FIFO_UNDERFLOW 0x08000000
> +#define DSI_FIFO_STATUS_DLN3_HS_FIFO_EMPTY 0x10000000
> +#define DSI_FIFO_STATUS_DLN3_HS_FIFO_FULL 0x20000000
> +#define DSI_FIFO_STATUS_DLN3_HS_FIFO_OVERFLOW 0x40000000
> +#define DSI_FIFO_STATUS_DLN3_HS_FIFO_UNDERFLOW 0x80000000
>
> #define REG_DSI_VID_CFG0 0x0000000c
> #define DSI_VID_CFG0_VIRT_CHANNEL__MASK 0x00000003
> @@ -318,38 +342,72 @@ static inline uint32_t DSI_CMD_CFG1_WR_MEM_CONTINUE(uint32_t val)
>
> #define REG_DSI_DMA_LEN 0x00000048
>
> -#define REG_DSI_CMD_MDP_STREAM_CTRL 0x00000054
> -#define DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK 0x0000003f
> -#define DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT 0
> -static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(uint32_t val)
> +#define REG_DSI_CMD_MDP_STREAM0_CTRL 0x00000054
> +#define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__MASK 0x0000003f
> +#define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__SHIFT 0
> +static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE(uint32_t val)
> {
> - return ((val) << DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK;
> + return ((val) << DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__MASK;
> }
> -#define DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
> -#define DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT 8
> -static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(uint32_t val)
> +#define DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
> +#define DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__SHIFT 8
> +static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL(uint32_t val)
> {
> - return ((val) << DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK;
> + return ((val) << DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__MASK;
> }
> -#define DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK 0xffff0000
> -#define DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT 16
> -static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(uint32_t val)
> +#define DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__MASK 0xffff0000
> +#define DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__SHIFT 16
> +static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(uint32_t val)
> {
> - return ((val) << DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK;
> + return ((val) << DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__MASK;
> }
>
> -#define REG_DSI_CMD_MDP_STREAM_TOTAL 0x00000058
> -#define DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK 0x00000fff
> -#define DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT 0
> -static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(uint32_t val)
> +#define REG_DSI_CMD_MDP_STREAM0_TOTAL 0x00000058
> +#define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__MASK 0x00000fff
> +#define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__SHIFT 0
> +static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(uint32_t val)
> {
> - return ((val) << DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK;
> + return ((val) << DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__MASK;
> }
> -#define DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK 0x0fff0000
> -#define DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT 16
> -static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(uint32_t val)
> +#define DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__MASK 0x0fff0000
> +#define DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__SHIFT 16
> +static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(uint32_t val)
> {
> - return ((val) << DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK;
> + return ((val) << DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__MASK;
> +}
> +
> +#define REG_DSI_CMD_MDP_STREAM1_CTRL 0x0000005c
> +#define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__MASK 0x0000003f
> +#define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__SHIFT 0
> +static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE(uint32_t val)
> +{
> + return ((val) << DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__MASK;
> +}
> +#define DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
> +#define DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__SHIFT 8
> +static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL(uint32_t val)
> +{
> + return ((val) << DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__MASK;
> +}
> +#define DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__MASK 0xffff0000
> +#define DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__SHIFT 16
> +static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT(uint32_t val)
> +{
> + return ((val) << DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__MASK;
> +}
> +
> +#define REG_DSI_CMD_MDP_STREAM1_TOTAL 0x00000060
> +#define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__MASK 0x0000ffff
> +#define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__SHIFT 0
> +static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL(uint32_t val)
> +{
> + return ((val) << DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__MASK;
> +}
> +#define DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__MASK 0xffff0000
> +#define DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__SHIFT 16
> +static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL(uint32_t val)
> +{
> + return ((val) << DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__MASK;
> }
>
> #define REG_DSI_ACK_ERR_STATUS 0x00000064
> @@ -389,6 +447,35 @@ static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val)
> #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 0x00001000
> #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1 0x00010000
>
> +#define REG_DSI_LP_TIMER_CTRL 0x000000b4
> +#define DSI_LP_TIMER_CTRL_LP_RX_TO__MASK 0x0000ffff
> +#define DSI_LP_TIMER_CTRL_LP_RX_TO__SHIFT 0
> +static inline uint32_t DSI_LP_TIMER_CTRL_LP_RX_TO(uint32_t val)
> +{
> + return ((val) << DSI_LP_TIMER_CTRL_LP_RX_TO__SHIFT) & DSI_LP_TIMER_CTRL_LP_RX_TO__MASK;
> +}
> +#define DSI_LP_TIMER_CTRL_BTA_TO__MASK 0xffff0000
> +#define DSI_LP_TIMER_CTRL_BTA_TO__SHIFT 16
> +static inline uint32_t DSI_LP_TIMER_CTRL_BTA_TO(uint32_t val)
> +{
> + return ((val) << DSI_LP_TIMER_CTRL_BTA_TO__SHIFT) & DSI_LP_TIMER_CTRL_BTA_TO__MASK;
> +}
> +
> +#define REG_DSI_HS_TIMER_CTRL 0x000000b8
> +#define DSI_HS_TIMER_CTRL_HS_TX_TO__MASK 0x0000ffff
> +#define DSI_HS_TIMER_CTRL_HS_TX_TO__SHIFT 0
> +static inline uint32_t DSI_HS_TIMER_CTRL_HS_TX_TO(uint32_t val)
> +{
> + return ((val) << DSI_HS_TIMER_CTRL_HS_TX_TO__SHIFT) & DSI_HS_TIMER_CTRL_HS_TX_TO__MASK;
> +}
> +#define DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__MASK 0x000f0000
> +#define DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__SHIFT 16
> +static inline uint32_t DSI_HS_TIMER_CTRL_TIMER_RESOLUTION(uint32_t val)
> +{
> + return ((val) << DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__SHIFT) & DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__MASK;
> +}
> +#define DSI_HS_TIMER_CTRL_HS_TX_TO_STOP_EN 0x10000000
> +
> #define REG_DSI_TIMEOUT_STATUS 0x000000bc
>
> #define REG_DSI_CLKOUT_TIMING_CTRL 0x000000c0
> @@ -409,6 +496,19 @@ static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val)
> #define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND 0x00000001
> #define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE 0x00000010
>
> +#define REG_DSI_LANE_STATUS 0x000000a4
> +#define DSI_LANE_STATUS_DLN0_STOPSTATE 0x00000001
> +#define DSI_LANE_STATUS_DLN1_STOPSTATE 0x00000002
> +#define DSI_LANE_STATUS_DLN2_STOPSTATE 0x00000004
> +#define DSI_LANE_STATUS_DLN3_STOPSTATE 0x00000008
> +#define DSI_LANE_STATUS_CLKLN_STOPSTATE 0x00000010
> +#define DSI_LANE_STATUS_DLN0_ULPS_ACTIVE_NOT 0x00000100
> +#define DSI_LANE_STATUS_DLN1_ULPS_ACTIVE_NOT 0x00000200
> +#define DSI_LANE_STATUS_DLN2_ULPS_ACTIVE_NOT 0x00000400
> +#define DSI_LANE_STATUS_DLN3_ULPS_ACTIVE_NOT 0x00000800
> +#define DSI_LANE_STATUS_CLKLN_ULPS_ACTIVE_NOT 0x00001000
> +#define DSI_LANE_STATUS_DLN0_DIRECTION 0x00010000
> +
> #define REG_DSI_LANE_CTRL 0x000000a8
> #define DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST 0x10000000
>
> @@ -436,6 +536,21 @@ static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val)
> #define DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK 0x00000200
>
> #define REG_DSI_CLK_STATUS 0x0000011c
> +#define DSI_CLK_STATUS_DSI_AON_AHBM_HCLK_ACTIVE 0x00000001
> +#define DSI_CLK_STATUS_DSI_DYN_AHBM_HCLK_ACTIVE 0x00000002
> +#define DSI_CLK_STATUS_DSI_AON_AHBS_HCLK_ACTIVE 0x00000004
> +#define DSI_CLK_STATUS_DSI_DYN_AHBS_HCLK_ACTIVE 0x00000008
> +#define DSI_CLK_STATUS_DSI_AON_DSICLK_ACTIVE 0x00000010
> +#define DSI_CLK_STATUS_DSI_DYN_DSICLK_ACTIVE 0x00000020
> +#define DSI_CLK_STATUS_DSI_AON_BYTECLK_ACTIVE 0x00000040
> +#define DSI_CLK_STATUS_DSI_DYN_BYTECLK_ACTIVE 0x00000080
> +#define DSI_CLK_STATUS_DSI_AON_ESCCLK_ACTIVE 0x00000100
> +#define DSI_CLK_STATUS_DSI_AON_PCLK_ACTIVE 0x00000200
> +#define DSI_CLK_STATUS_DSI_DYN_PCLK_ACTIVE 0x00000400
> +#define DSI_CLK_STATUS_DSI_DYN_CMD_PCLK_ACTIVE 0x00001000
> +#define DSI_CLK_STATUS_DSI_CMD_PCLK_ACTIVE 0x00002000
> +#define DSI_CLK_STATUS_DSI_VID_PCLK_ACTIVE 0x00004000
> +#define DSI_CLK_STATUS_DSI_CAM_BIST_PCLK_ACT 0x00008000
> #define DSI_CLK_STATUS_PLL_UNLOCKED 0x00010000
>
> #define REG_DSI_PHY_RESET 0x00000128
> @@ -444,6 +559,51 @@ static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val)
> #define REG_DSI_T_CLK_PRE_EXTEND 0x0000017c
> #define DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK 0x00000001
>
> +#define REG_DSI_CMD_MODE_MDP_CTRL2 0x000001b4
> +#define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__MASK 0x0000000f
> +#define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__SHIFT 0
> +static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2(enum dsi_cmd_dst_format val)
> +{
> + return ((val) << DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__MASK;
> +}
> +#define DSI_CMD_MODE_MDP_CTRL2_R_SEL 0x00000010
> +#define DSI_CMD_MODE_MDP_CTRL2_G_SEL 0x00000020
> +#define DSI_CMD_MODE_MDP_CTRL2_B_SEL 0x00000040
> +#define DSI_CMD_MODE_MDP_CTRL2_BYTE_MSB_LSB_FLIP 0x00000080
> +#define DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__MASK 0x00000700
> +#define DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__SHIFT 8
> +static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP(enum dsi_rgb_swap val)
> +{
> + return ((val) << DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__MASK;
> +}
> +#define DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK 0x00007000
> +#define DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT 12
> +static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP(enum dsi_rgb_swap val)
> +{
> + return ((val) << DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK;
> +}
> +#define DSI_CMD_MODE_MDP_CTRL2_BURST_MODE 0x00010000
> +
> +#define REG_DSI_CMD_MODE_MDP_STREAM2_CTRL 0x000001b8
> +#define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK 0x0000003f
> +#define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__SHIFT 0
> +static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE(uint32_t val)
> +{
> + return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK;
> +}
> +#define DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
> +#define DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__SHIFT 8
> +static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL(uint32_t val)
> +{
> + return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__MASK;
> +}
> +#define DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__MASK 0xffff0000
> +#define DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__SHIFT 16
> +static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT(uint32_t val)
> +{
> + return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__MASK;
> +}
> +
> #define REG_DSI_RDBK_DATA_CTRL 0x000001d0
> #define DSI_RDBK_DATA_CTRL_COUNT__MASK 0x00ff0000
> #define DSI_RDBK_DATA_CTRL_COUNT__SHIFT 16
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 813f44fada39..c8b54998c42c 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -986,16 +986,16 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_dual_dsi)
> /* image data and 1 byte write_memory_start cmd */
> wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
>
> - dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_CTRL,
> - DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(wc) |
> - DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(
> + dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL,
> + DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) |
> + DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL(
> msm_host->channel) |
> - DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(
> + DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE(
> MIPI_DSI_DCS_LONG_WRITE));
>
> - dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_TOTAL,
> - DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(hdisplay) |
> - DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(mode->vdisplay));
> + dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL,
> + DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) |
> + DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay));
> }
> }
>
> diff --git a/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h b/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
> index 874265314413..ac290a74185a 100644
> --- a/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
> +++ b/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
> @@ -13,7 +13,7 @@ The rules-ng-ng source files this header was generated from are:
> - /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-07-03 19:37:13)
> +- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-04 21:03:00)
> - /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2018-07-03 19:37:13)
> diff --git a/drivers/gpu/drm/msm/dsi/sfpb.xml.h b/drivers/gpu/drm/msm/dsi/sfpb.xml.h
> index 07c48ddb5301..433c4f330744 100644
> --- a/drivers/gpu/drm/msm/dsi/sfpb.xml.h
> +++ b/drivers/gpu/drm/msm/dsi/sfpb.xml.h
> @@ -13,7 +13,7 @@ The rules-ng-ng source files this header was generated from are:
> - /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-07-03 19:37:13)
> +- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-04 21:03:00)
> - /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2018-07-03 19:37:13)
> diff --git a/drivers/gpu/drm/msm/edp/edp.xml.h b/drivers/gpu/drm/msm/edp/edp.xml.h
> index 9cb6e6fe9810..4281253af269 100644
> --- a/drivers/gpu/drm/msm/edp/edp.xml.h
> +++ b/drivers/gpu/drm/msm/edp/edp.xml.h
> @@ -13,7 +13,7 @@ The rules-ng-ng source files this header was generated from are:
> - /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-07-03 19:37:13)
> +- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-04 21:03:00)
> - /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2018-07-03 19:37:13)
> diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
> index 3eff3ea3b271..5f8cdf581ba6 100644
> --- a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
> +++ b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
> @@ -13,7 +13,7 @@ The rules-ng-ng source files this header was generated from are:
> - /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-07-03 19:37:13)
> +- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-04 21:03:00)
> - /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2018-07-03 19:37:13)
> diff --git a/drivers/gpu/drm/msm/hdmi/qfprom.xml.h b/drivers/gpu/drm/msm/hdmi/qfprom.xml.h
> index 7717d4269662..fc3a852a8cda 100644
> --- a/drivers/gpu/drm/msm/hdmi/qfprom.xml.h
> +++ b/drivers/gpu/drm/msm/hdmi/qfprom.xml.h
> @@ -13,7 +13,7 @@ The rules-ng-ng source files this header was generated from are:
> - /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2018-07-03 19:37:13)
> -- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-07-03 19:37:13)
> +- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-04 21:03:00)
> - /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2018-07-03 19:37:13)
> --
> 2.26.2
>
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2020-07-10 18:03 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-07 20:34 [PATCH 0/2] drm/msm/adreno: cleanup some packet building Rob Clark
2020-07-07 20:34 ` Rob Clark
2020-07-07 20:34 ` [PATCH 1/2] drm/msm: sync generated headers Rob Clark
2020-07-07 20:34 ` Rob Clark
2020-07-10 18:02 ` Jordan Crouse [this message]
2020-07-11 11:48 ` Linus Walleij
2020-07-11 11:48 ` Linus Walleij
2020-07-11 14:49 ` Rob Clark
2020-07-11 14:49 ` Rob Clark
2020-07-07 20:35 ` [PATCH 2/2] drm/msm/adreno: un-open-code some packets Rob Clark
2020-07-07 20:35 ` Rob Clark
2020-07-10 18:03 ` [Freedreno] " Jordan Crouse
2020-07-10 18:03 ` Jordan Crouse
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