From: Alexandru Ardelean <alexandru.ardelean@analog.com>
To: <linux-clk@vger.kernel.org>, <linux-fpga@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Cc: <mturquette@baylibre.com>, <sboyd@kernel.org>, <mdf@kernel.org>,
<ardeleanalex@gmail.com>,
Dragos Bogdan <dragos.bogdan@analog.com>,
"Alexandru Ardelean" <alexandru.ardelean@analog.com>
Subject: [PATCH v2 3/6] clk: axi-clkgen: add support for ZynqMP (UltraScale)
Date: Mon, 10 Aug 2020 16:42:42 +0300 [thread overview]
Message-ID: <20200810134252.68614-4-alexandru.ardelean@analog.com> (raw)
In-Reply-To: <20200810134252.68614-1-alexandru.ardelean@analog.com>
From: Dragos Bogdan <dragos.bogdan@analog.com>
This IP core also works and is supported on the Xilinx ZynqMP (UltraScale)
FPGA boards.
This patch enables the driver to be available on these platforms as well.
Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
---
drivers/clk/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 69934c0c3dd8..eaabc758a7e4 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -240,7 +240,7 @@ config CLK_TWL6040
config COMMON_CLK_AXI_CLKGEN
tristate "AXI clkgen driver"
- depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST
+ depends on ARCH_ZYNQ || ARCH_ZYNQMP || MICROBLAZE || COMPILE_TEST
help
Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
FPGAs. It is commonly used in Analog Devices' reference designs.
--
2.17.1
next prev parent reply other threads:[~2020-08-10 13:41 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-10 13:42 [PATCH v2 0/6] clk: axi-clk-gen: misc updates to the driver Alexandru Ardelean
2020-08-10 13:42 ` [PATCH v2 1/6] clk: axi-clkgen: Add support for fractional dividers Alexandru Ardelean
2020-08-10 13:42 ` [PATCH v2 2/6] clk: axi-clkgen: Set power bits for fractional mode Alexandru Ardelean
2020-08-10 13:42 ` Alexandru Ardelean [this message]
2020-08-10 13:42 ` [PATCH v2 4/6] clk: axi-clkgen: Respect ZYNQMP PFD/VCO frequency limits Alexandru Ardelean
2020-08-10 13:42 ` [PATCH v2 5/6] include: fpga: adi-axi-common.h: add definitions for supported FPGAs Alexandru Ardelean
2020-08-10 14:07 ` Tom Rix
2020-09-14 21:46 ` Moritz Fischer
2020-08-10 13:42 ` [PATCH v2 6/6] clk: axi-clkgen: Add support for FPGA info Alexandru Ardelean
2020-08-10 13:42 ` [PATCH v2 0/6] clk: axi-clk-gen: misc updates to the driver Alexandru Ardelean
2020-09-14 8:11 ` Alexandru Ardelean
2020-09-15 2:41 ` Moritz Fischer
2020-09-22 19:42 ` Stephen Boyd
2020-09-23 6:22 ` Alexandru Ardelean
2020-09-23 23:58 ` Stephen Boyd
2020-09-24 4:53 ` Moritz Fischer
2020-09-24 5:41 ` Alexandru Ardelean
2020-08-10 13:42 ` [PATCH v2 1/6] clk: axi-clkgen: Add support for fractional dividers Alexandru Ardelean
2020-08-10 13:42 ` [PATCH v2 2/6] clk: axi-clkgen: Set power bits for fractional mode Alexandru Ardelean
2020-08-10 13:42 ` [PATCH v2 3/6] clk: axi-clkgen: add support for ZynqMP (UltraScale) Alexandru Ardelean
2020-08-10 13:42 ` [PATCH v2 4/6] clk: axi-clkgen: Respect ZYNQMP PFD/VCO frequency limits Alexandru Ardelean
2020-08-10 13:42 ` [PATCH v2 5/6] include: fpga: adi-axi-common.h: add definitions for supported FPGAs Alexandru Ardelean
2020-08-10 13:42 ` [PATCH v2 6/6] clk: axi-clkgen: Add support for FPGA info Alexandru Ardelean
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