Re: [Intel-gfx] [PATCH v3] drm/i915/gt: Implement WA_1406941453

From: Matt Roper <matthew.d.roper@intel.com>
To: clinton.a.taylor@intel.com
Cc: Intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v3] drm/i915/gt: Implement WA_1406941453
Date: Tue, 25 Aug 2020 15:11:17 -0700	[thread overview]
Message-ID: <20200825221117.GI3934000@mdroper-desk1.amr.corp.intel.com> (raw)
In-Reply-To: <20200825215434.6009-1-clinton.a.taylor@intel.com>

On Tue, Aug 25, 2020 at 02:54:34PM -0700, clinton.a.taylor@intel.com wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
> 
> Enable HW Default flip for small PL.
> 
> bspec: 52890
> bspec: 53508
> bspec: 53273
> 
> v2: rebase to drm-tip
> v3: move from ctx to gt workarounds. Remove whitelist.

I think we actually want to move this one to the rcs_engine_wa_init()
since the register appears to be part of the render engine specifically.
Since this register doesn't hold its value across engine resets[*] we
want to re-apply the workaround any time the RCS engine is reset.

[*] There's been a bit of ambiguity and confusion about what registers
do/don't survive engine resets, but we're starting to get more clarity
on that from the hardware teams now.  There's usually a field in the
bspec's register description that says "GTIReset" --- if that says "DEV"
it's an engine register that should be handled in rcs_engine_wa_init (or
xcs_engine_wa_init for other engine types), whereas if it says "BUS"
it's a GT register that should go in gt_workarounds_init.

Matt

> 
> Cc: Matt Atwood <matthew.s.atwood@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
>  drivers/gpu/drm/i915/i915_reg.h             | 1 +
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index a3f72b75c61e..0aecb97fd41c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1211,6 +1211,9 @@ gen12_gt_workarounds_init(struct drm_i915_private *i915,
>  			  struct i915_wa_list *wal)
>  {
>  	wa_init_mcr(i915, wal);
> +
> +	/* Wa_1406941453:gen12 */
> +	WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE, ENABLE_SMALLPL);
>  }
>  
>  static void
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ac691927e29d..ab4b1abd4364 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9315,6 +9315,7 @@ enum {
>  #define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC	(1 << 7)
>  
>  #define GEN10_SAMPLER_MODE		_MMIO(0xE18C)
> +#define   ENABLE_SMALLPL			REG_BIT(15)
>  #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG	REG_BIT(5)
>  
>  /* IVYBRIDGE DPF */
> -- 
> 2.28.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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