From: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, bhelgaas@google.com,
robh+dt@kernel.org, shawnguo@kernel.org, leoyang.li@nxp.com,
lorenzo.pieralisi@arm.com, gustavo.pimentel@synopsys.com
Cc: minghuan.Lian@nxp.com, mingkai.hu@nxp.com, roy.zang@nxp.com,
Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Subject: [PATCH 3/7] dt-bindings: pci: layerscape-pci: Add a optional property big-endian
Date: Mon, 7 Sep 2020 13:37:57 +0800 [thread overview]
Message-ID: <20200907053801.22149-4-Zhiqiang.Hou@nxp.com> (raw)
In-Reply-To: <20200907053801.22149-1-Zhiqiang.Hou@nxp.com>
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
This property is to indicate the endianness when accessing the
PEX_LUT and PF register block, so if these registers are
implemented in big-endian, specify this property.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index 99a386ea691c..2236d3f3089b 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -37,6 +37,10 @@ Required properties:
of the data transferred from/to the IP block. This can avoid the software
cache flush/invalid actions, and improve the performance significantly.
+Optional properties:
+- big-endian: If the PEX_LUT and PF register block is in big-endian, specify
+ this property.
+
Example:
pcie@3400000 {
--
2.17.1
next prev parent reply other threads:[~2020-09-07 5:46 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-07 5:37 [PATCH 0/7] PCI: layerscape: Add power management support Zhiqiang Hou
2020-09-07 5:37 ` [PATCH 1/7] PCI: dwc: Fix a bug of the case dw_pci->ops is NULL Zhiqiang Hou
2020-09-09 9:28 ` Gustavo Pimentel
2020-09-13 16:17 ` Z.q. Hou
2020-09-15 1:16 ` Rob Herring
2020-09-15 3:39 ` Z.q. Hou
2020-09-07 5:37 ` [PATCH 2/7] PCI: layerscape: Change to use the DWC common link-up check function Zhiqiang Hou
2020-09-15 1:19 ` Rob Herring
2020-09-15 6:22 ` Z.q. Hou
2020-09-07 5:37 ` Zhiqiang Hou [this message]
2020-09-15 1:30 ` [PATCH 3/7] dt-bindings: pci: layerscape-pci: Add a optional property big-endian Rob Herring
2020-09-15 3:39 ` Z.q. Hou
2020-09-07 5:37 ` [PATCH 4/7] arm64: dts: layerscape: Add big-endian property for PCIe nodes Zhiqiang Hou
2020-09-07 5:37 ` [PATCH 5/7] dt-bindings: pci: layerscape-pci: Update the description of SCFG property Zhiqiang Hou
2020-09-15 1:31 ` Rob Herring
2020-09-15 3:39 ` Z.q. Hou
2020-09-07 5:38 ` [PATCH 6/7] dts: arm64: ls1043a: Add SCFG phandle for PCIe nodes Zhiqiang Hou
2020-09-21 13:16 ` Shawn Guo
2020-09-21 16:46 ` Z.q. Hou
2020-09-07 5:38 ` [PATCH 7/7] PCI: layerscape: Add power management support Zhiqiang Hou
2020-09-15 1:30 ` Rob Herring
2020-09-15 6:44 ` Z.q. Hou
2021-03-23 11:15 ` [PATCH 0/7] " Lorenzo Pieralisi
2021-03-24 4:10 ` Z.q. Hou
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