From: Bjorn Helgaas <helgaas@kernel.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: agross@kernel.org, bjorn.andersson@linaro.org, kishon@ti.com,
vkoul@kernel.org, robh@kernel.org, svarbanov@mm-sol.com,
bhelgaas@google.com, lorenzo.pieralisi@arm.com,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, mgautam@codeaurora.org,
devicetree@vger.kernel.org, Jonathan Marek <jonathan@marek.ca>
Subject: Re: [PATCH 5/5] pci: controller: dwc: qcom: Harcode PCIe config SID
Date: Wed, 16 Sep 2020 17:06:18 -0500 [thread overview]
Message-ID: <20200916220618.GA1589351@bjorn-Precision-5520> (raw)
In-Reply-To: <20200916132000.1850-6-manivannan.sadhasivam@linaro.org>
s/Harcode/Hardcode/ (in subject)
Also fix subject format as for 4/5.
On Wed, Sep 16, 2020 at 06:50:00PM +0530, Manivannan Sadhasivam wrote:
> Hardcode the PCIe config SID table value. This is needed to avoid random
> MHI failure observed during reboot on SM8250.
>
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> [mani: stripped out unnecessary settings and ported for upstream]
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index ca8ad354e09d..50748016ce96 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -57,6 +57,7 @@
> #define PCIE20_PARF_SID_OFFSET 0x234
> #define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C
> #define PCIE20_PARF_DEVICE_TYPE 0x1000
> +#define PCIE20_PARF_BDF_TO_SID_TABLE_N 0x2000
>
> #define PCIE20_ELBI_SYS_CTRL 0x04
> #define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0)
> @@ -1290,6 +1291,9 @@ static int qcom_pcie_host_init(struct pcie_port *pp)
> if (ret)
> goto err;
>
> + writel(0x0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N);
> + writel(0x01000100, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N + 0x054);
> +
> return 0;
> err:
> qcom_ep_reset_assert(pcie);
> --
> 2.17.1
>
next prev parent reply other threads:[~2020-09-16 22:06 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-16 13:19 [PATCH 0/5] Add PCIe support for SM8250 SoC Manivannan Sadhasivam
2020-09-16 13:19 ` [PATCH 1/5] dt-bindings: phy: qcom,qmp: Document SM8250 PCIe PHY bindings Manivannan Sadhasivam
2020-09-16 22:45 ` Bjorn Andersson
2020-09-17 4:32 ` Vinod Koul
2020-09-17 5:10 ` Bjorn Andersson
2020-09-16 13:19 ` [PATCH 2/5] phy: qualcomm: phy-qcom-qmp: Add PCIe PHY support for SM8250 SoC Manivannan Sadhasivam
2020-09-16 22:53 ` Bjorn Andersson
2020-09-17 4:49 ` Vinod Koul
2020-09-16 13:19 ` [PATCH 3/5] dt-bindings: pci: qcom: Document PCIe bindings " Manivannan Sadhasivam
2020-09-16 22:55 ` Bjorn Andersson
2020-09-16 13:19 ` [PATCH 4/5] pci: controller: dwc: qcom: Add PCIe support " Manivannan Sadhasivam
2020-09-16 22:04 ` Bjorn Helgaas
2020-09-23 15:58 ` Rob Herring
2020-09-16 13:20 ` [PATCH 5/5] pci: controller: dwc: qcom: Harcode PCIe config SID Manivannan Sadhasivam
2020-09-16 22:06 ` Bjorn Helgaas [this message]
2020-09-17 0:39 ` Bjorn Andersson
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