From: Andy Shevchenko <andy.shevchenko@gmail.com>
To: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Mark Brown <broonie@kernel.org>,
Serge Semin <fancer.lancer@gmail.com>,
Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>,
Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>,
Lars Povlsen <lars.povlsen@microchip.com>,
"wuxu . wu" <wuxu.wu@huawei.com>, Feng Tang <feng.tang@intel.com>,
Rob Herring <robh+dt@kernel.org>,
linux-spi@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 00/21] spi: dw: Add full Baikal-T1 SPI Controllers support
Date: Fri, 2 Oct 2020 13:24:44 +0300 [thread overview]
Message-ID: <20201002102444.GY3956970@smile.fi.intel.com> (raw)
In-Reply-To: <20201001222829.15977-1-Sergey.Semin@baikalelectronics.ru>
On Fri, Oct 02, 2020 at 01:28:08AM +0300, Serge Semin wrote:
> Originally I intended to merge a dedicated Baikal-T1 System Boot SPI
> Controller driver into the kernel and leave the DW APB SSI driver
> untouched. But after a long discussion (see the link at the bottom of the
> letter) Mark and Andy persuaded me to integrate what we developed there
> into the DW APB SSI core driver to be useful for another controllers,
> which may have got the same peculiarities/problems as ours:
> - No IRQ.
> - No DMA.
> - No GPIO CS, so a native CS is utilized.
> - small Tx/Rx FIFO depth.
> - Automatic CS assertion/de-assertion.
> - Slow system bus.
> All of them have been fixed in the framework of this patchset in some
> extent at least for the SPI memory operations. As I expected it wasn't
> that easy and the integration took that many patches as you can see from
> the subject. Though some of them are mere cleanups or weakly related with
> the subject fixes, but we just couldn't leave the code as is at some
> places since we were working with the DW APB SSI driver anyway. Here is
> what we did to fix the original DW APB SSI driver, to make it less messy.
Maybe it's time to put your name into MAINTAINERS for this driver?
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2020-10-02 10:25 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-01 22:28 [PATCH v3 00/21] spi: dw: Add full Baikal-T1 SPI Controllers support Serge Semin
2020-10-01 22:28 ` [PATCH v3 01/21] spi: dw: Use an explicit set_cs assignment Serge Semin
2020-10-01 22:28 ` [PATCH v3 02/21] spi: dw: Add DWC SSI capability Serge Semin
2020-10-02 10:19 ` Andy Shevchenko
2020-10-02 17:18 ` Serge Semin
2020-10-02 18:26 ` Andy Shevchenko
2020-10-02 19:46 ` Serge Semin
2020-10-02 20:08 ` Serge Semin
2020-10-02 20:12 ` Serge Semin
2020-10-01 22:28 ` [PATCH v3 03/21] spi: dw: Detach SPI device specific CR0 config method Serge Semin
2020-10-02 10:22 ` Andy Shevchenko
2020-10-02 17:47 ` Serge Semin
2020-10-02 18:24 ` Andy Shevchenko
2020-10-02 19:56 ` Serge Semin
2020-10-01 22:28 ` [PATCH v3 04/21] spi: dw: Update SPI bus speed in a config function Serge Semin
2020-10-01 22:28 ` [PATCH v3 05/21] spi: dw: Simplify the SPI bus speed config procedure Serge Semin
2020-10-01 22:28 ` [PATCH v3 06/21] spi: dw: Update Rx sample delay in the config function Serge Semin
2020-10-01 22:28 ` [PATCH v3 07/21] spi: dw: Add DW SPI controller config structure Serge Semin
2020-10-01 22:28 ` [PATCH v3 08/21] spi: dw: Refactor data IO procedure Serge Semin
2020-10-01 22:28 ` [PATCH v3 09/21] spi: dw: Refactor IRQ-based SPI transfer procedure Serge Semin
2020-10-01 22:28 ` [PATCH v3 10/21] spi: dw: Perform IRQ setup in a dedicated function Serge Semin
2020-10-01 22:28 ` [PATCH v3 11/21] spi: dw: Unmask IRQs after enabling the chip Serge Semin
2020-10-01 22:28 ` [PATCH v3 12/21] spi: dw: Discard chip enabling on DMA setup error Serge Semin
2020-10-01 22:28 ` [PATCH v3 13/21] spi: dw: De-assert chip-select on reset Serge Semin
2020-10-01 22:28 ` [PATCH v3 14/21] spi: dw: Explicitly de-assert CS on SPI transfer completion Serge Semin
2020-10-01 22:28 ` [PATCH v3 15/21] spi: dw: Move num-of retries parameter to the header file Serge Semin
2020-10-01 22:28 ` [PATCH v3 16/21] spi: dw: Add generic DW SSI status-check method Serge Semin
2020-10-01 22:28 ` [PATCH v3 17/21] spi: dw: Add memory operations support Serge Semin
2020-10-01 22:28 ` [PATCH v3 18/21] spi: dw: Introduce max mem-ops SPI bus frequency setting Serge Semin
2020-10-01 22:28 ` [PATCH v3 19/21] spi: dw: Add poll-based SPI transfers support Serge Semin
2020-10-01 22:28 ` [PATCH v3 20/21] dt-bindings: spi: dw: Add Baikal-T1 SPI Controllers Serge Semin
2020-10-01 22:28 ` [PATCH v3 21/21] spi: dw: Add Baikal-T1 SPI Controller glue driver Serge Semin
2020-10-02 10:24 ` Andy Shevchenko [this message]
2020-10-02 12:55 ` [PATCH v3 00/21] spi: dw: Add full Baikal-T1 SPI Controllers support Mark Brown
2020-10-02 18:26 ` Andy Shevchenko
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20201002102444.GY3956970@smile.fi.intel.com \
--to=andy.shevchenko@gmail.com \
--cc=Alexey.Malahov@baikalelectronics.ru \
--cc=Pavel.Parkhomenko@baikalelectronics.ru \
--cc=Ramil.Zaripov@baikalelectronics.ru \
--cc=Sergey.Semin@baikalelectronics.ru \
--cc=broonie@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=fancer.lancer@gmail.com \
--cc=feng.tang@intel.com \
--cc=lars.povlsen@microchip.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-spi@vger.kernel.org \
--cc=robh+dt@kernel.org \
--cc=wuxu.wu@huawei.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.