From: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
To: herbert@gondor.apana.org.au
Cc: linux-crypto@vger.kernel.org, qat-linux@intel.com,
Giovanni Cabiddu <giovanni.cabiddu@intel.com>,
Fiona Trahe <fiona.trahe@intel.com>,
Wojciech Ziemba <wojciech.ziemba@intel.com>,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Subject: [PATCH 07/31] crypto: qat - abstract admin interface
Date: Mon, 12 Oct 2020 21:38:23 +0100 [thread overview]
Message-ID: <20201012203847.340030-8-giovanni.cabiddu@intel.com> (raw)
In-Reply-To: <20201012203847.340030-1-giovanni.cabiddu@intel.com>
Abstract access to admin interface and move generation specific code into
adf_gen2_hw_data.c in preparation for the introduction of the qat_4xxx
driver.
Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Reviewed-by: Fiona Trahe <fiona.trahe@intel.com>
Reviewed-by: Wojciech Ziemba <wojciech.ziemba@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
.../crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c | 1 +
.../crypto/qat/qat_c62x/adf_c62x_hw_data.c | 1 +
.../crypto/qat/qat_common/adf_accel_devices.h | 7 ++++++
drivers/crypto/qat/qat_common/adf_admin.c | 25 +++++++++++--------
.../crypto/qat/qat_common/adf_gen2_hw_data.c | 8 ++++++
.../crypto/qat/qat_common/adf_gen2_hw_data.h | 6 +++++
.../qat/qat_dh895xcc/adf_dh895xcc_hw_data.c | 1 +
7 files changed, 39 insertions(+), 10 deletions(-)
diff --git a/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c b/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c
index 7af38b947cfe..f72ed415800e 100644
--- a/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c
+++ b/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c
@@ -202,6 +202,7 @@ void adf_init_hw_data_c3xxx(struct adf_hw_device_data *hw_data)
hw_data->get_misc_bar_id = get_misc_bar_id;
hw_data->get_pf2vf_offset = get_pf2vf_offset;
hw_data->get_vintmsk_offset = get_vintmsk_offset;
+ hw_data->get_admin_info = adf_gen2_get_admin_info;
hw_data->get_sku = get_sku;
hw_data->fw_name = ADF_C3XXX_FW;
hw_data->fw_mmp_name = ADF_C3XXX_MMP;
diff --git a/drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c b/drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c
index c18fb77dd8ec..d4443523dc9d 100644
--- a/drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c
+++ b/drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c
@@ -212,6 +212,7 @@ void adf_init_hw_data_c62x(struct adf_hw_device_data *hw_data)
hw_data->get_misc_bar_id = get_misc_bar_id;
hw_data->get_pf2vf_offset = get_pf2vf_offset;
hw_data->get_vintmsk_offset = get_vintmsk_offset;
+ hw_data->get_admin_info = adf_gen2_get_admin_info;
hw_data->get_sku = get_sku;
hw_data->fw_name = ADF_C62X_FW;
hw_data->fw_mmp_name = ADF_C62X_MMP;
diff --git a/drivers/crypto/qat/qat_common/adf_accel_devices.h b/drivers/crypto/qat/qat_common/adf_accel_devices.h
index 459e22076813..5f57850c2e8d 100644
--- a/drivers/crypto/qat/qat_common/adf_accel_devices.h
+++ b/drivers/crypto/qat/qat_common/adf_accel_devices.h
@@ -97,6 +97,12 @@ struct adf_hw_device_class {
u32 instances;
} __packed;
+struct admin_info {
+ u32 admin_msg_ur;
+ u32 admin_msg_lr;
+ u32 mailbox_offset;
+};
+
struct adf_hw_csr_ops {
u32 (*read_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,
u32 ring);
@@ -138,6 +144,7 @@ struct adf_hw_device_data {
u32 (*get_num_accels)(struct adf_hw_device_data *self);
u32 (*get_pf2vf_offset)(u32 i);
u32 (*get_vintmsk_offset)(u32 i);
+ void (*get_admin_info)(struct admin_info *admin_csrs_info);
enum dev_sku_info (*get_sku)(struct adf_hw_device_data *self);
int (*alloc_irq)(struct adf_accel_dev *accel_dev);
void (*free_irq)(struct adf_accel_dev *accel_dev);
diff --git a/drivers/crypto/qat/qat_common/adf_admin.c b/drivers/crypto/qat/qat_common/adf_admin.c
index ec9b390276d6..3ae7c89ce82a 100644
--- a/drivers/crypto/qat/qat_common/adf_admin.c
+++ b/drivers/crypto/qat/qat_common/adf_admin.c
@@ -10,11 +10,7 @@
#include "adf_common_drv.h"
#include "icp_qat_fw_init_admin.h"
-/* Admin Messages Registers */
-#define ADF_DH895XCC_ADMINMSGUR_OFFSET (0x3A000 + 0x574)
-#define ADF_DH895XCC_ADMINMSGLR_OFFSET (0x3A000 + 0x578)
-#define ADF_DH895XCC_MAILBOX_BASE_OFFSET 0x20970
-#define ADF_DH895XCC_MAILBOX_STRIDE 0x1000
+#define ADF_ADMIN_MAILBOX_STRIDE 0x1000
#define ADF_ADMINMSG_LEN 32
#define ADF_CONST_TABLE_SIZE 1024
#define ADF_ADMIN_POLL_DELAY_US 20
@@ -118,7 +114,7 @@ static int adf_put_admin_msg_sync(struct adf_accel_dev *accel_dev, u32 ae,
struct adf_admin_comms *admin = accel_dev->admin;
int offset = ae * ADF_ADMINMSG_LEN * 2;
void __iomem *mailbox = admin->mailbox_addr;
- int mb_offset = ae * ADF_DH895XCC_MAILBOX_STRIDE;
+ int mb_offset = ae * ADF_ADMIN_MAILBOX_STRIDE;
struct icp_qat_fw_init_admin_req *request = in;
mutex_lock(&admin->lock);
@@ -225,8 +221,9 @@ int adf_init_admin_comms(struct adf_accel_dev *accel_dev)
struct adf_bar *pmisc =
&GET_BARS(accel_dev)[hw_data->get_misc_bar_id(hw_data)];
void __iomem *csr = pmisc->virt_addr;
- void __iomem *mailbox = (void __iomem *)((uintptr_t)csr +
- ADF_DH895XCC_MAILBOX_BASE_OFFSET);
+ struct admin_info admin_csrs_info;
+ u32 mailbox_offset, adminmsg_u, adminmsg_l;
+ void __iomem *mailbox;
u64 reg_val;
admin = kzalloc_node(sizeof(*accel_dev->admin), GFP_KERNEL,
@@ -254,9 +251,17 @@ int adf_init_admin_comms(struct adf_accel_dev *accel_dev)
}
memcpy(admin->virt_tbl_addr, const_tab, sizeof(const_tab));
+ hw_data->get_admin_info(&admin_csrs_info);
+
+ mailbox_offset = admin_csrs_info.mailbox_offset;
+ mailbox = (void __iomem *)((uintptr_t)csr + mailbox_offset);
+ adminmsg_u = admin_csrs_info.admin_msg_ur;
+ adminmsg_l = admin_csrs_info.admin_msg_lr;
+
reg_val = (u64)admin->phy_addr;
- ADF_CSR_WR(csr, ADF_DH895XCC_ADMINMSGUR_OFFSET, reg_val >> 32);
- ADF_CSR_WR(csr, ADF_DH895XCC_ADMINMSGLR_OFFSET, reg_val);
+ ADF_CSR_WR(csr, adminmsg_u, upper_32_bits(reg_val));
+ ADF_CSR_WR(csr, adminmsg_l, lower_32_bits(reg_val));
+
mutex_init(&admin->lock);
admin->mailbox_addr = mailbox;
accel_dev->admin = admin;
diff --git a/drivers/crypto/qat/qat_common/adf_gen2_hw_data.c b/drivers/crypto/qat/qat_common/adf_gen2_hw_data.c
index 9011c94156a9..15a0bc921d7e 100644
--- a/drivers/crypto/qat/qat_common/adf_gen2_hw_data.c
+++ b/drivers/crypto/qat/qat_common/adf_gen2_hw_data.c
@@ -37,6 +37,14 @@ void adf_gen2_cfg_iov_thds(struct adf_accel_dev *accel_dev, bool enable,
}
EXPORT_SYMBOL_GPL(adf_gen2_cfg_iov_thds);
+void adf_gen2_get_admin_info(struct admin_info *admin_csrs_info)
+{
+ admin_csrs_info->mailbox_offset = ADF_MAILBOX_BASE_OFFSET;
+ admin_csrs_info->admin_msg_ur = ADF_ADMINMSGUR_OFFSET;
+ admin_csrs_info->admin_msg_lr = ADF_ADMINMSGLR_OFFSET;
+}
+EXPORT_SYMBOL_GPL(adf_gen2_get_admin_info);
+
static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring)
{
return READ_CSR_RING_HEAD(csr_base_addr, bank, ring);
diff --git a/drivers/crypto/qat/qat_common/adf_gen2_hw_data.h b/drivers/crypto/qat/qat_common/adf_gen2_hw_data.h
index 592aee627762..e9d2591b2be8 100644
--- a/drivers/crypto/qat/qat_common/adf_gen2_hw_data.h
+++ b/drivers/crypto/qat/qat_common/adf_gen2_hw_data.h
@@ -92,8 +92,14 @@ do { \
ADF_CSR_WR(pmisc_bar_addr, AE2FUNCTION_MAP_B_OFFSET + \
AE2FUNCTION_MAP_REG_SIZE * (index), value)
+/* Admin Interface Offsets */
+#define ADF_ADMINMSGUR_OFFSET (0x3A000 + 0x574)
+#define ADF_ADMINMSGLR_OFFSET (0x3A000 + 0x578)
+#define ADF_MAILBOX_BASE_OFFSET 0x20970
+
void adf_gen2_cfg_iov_thds(struct adf_accel_dev *accel_dev, bool enable,
int num_a_regs, int num_b_regs);
void adf_gen2_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops);
+void adf_gen2_get_admin_info(struct admin_info *admin_csrs_info);
#endif
diff --git a/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c b/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
index 39423316664b..c568e9808cec 100644
--- a/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
+++ b/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
@@ -210,6 +210,7 @@ void adf_init_hw_data_dh895xcc(struct adf_hw_device_data *hw_data)
hw_data->get_misc_bar_id = get_misc_bar_id;
hw_data->get_pf2vf_offset = get_pf2vf_offset;
hw_data->get_vintmsk_offset = get_vintmsk_offset;
+ hw_data->get_admin_info = adf_gen2_get_admin_info;
hw_data->get_sram_bar_id = get_sram_bar_id;
hw_data->get_sku = get_sku;
hw_data->fw_name = ADF_DH895XCC_FW;
--
2.26.2
next prev parent reply other threads:[~2020-10-12 20:39 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-12 20:38 [PATCH 00/31] crypto: qat - rework in preparation for qat_4xxx driver Giovanni Cabiddu
2020-10-12 20:38 ` [PATCH 01/31] crypto: qat - update IV in software Giovanni Cabiddu
2020-10-12 20:38 ` [PATCH 02/31] crypto: qat - mask device capabilities with soft straps Giovanni Cabiddu
2020-10-12 20:38 ` [PATCH 03/31] crypto: qat - num_rings_per_bank is device dependent Giovanni Cabiddu
2020-10-12 20:38 ` [PATCH 04/31] crypto: qat - fix configuration of iov threads Giovanni Cabiddu
2020-10-12 20:38 ` [PATCH 05/31] crypto: qat - split transport CSR access logic Giovanni Cabiddu
2020-10-12 20:38 ` [PATCH 06/31] crypto: qat - relocate GEN2 CSR access code Giovanni Cabiddu
2020-10-12 20:38 ` Giovanni Cabiddu [this message]
2020-10-12 20:38 ` [PATCH 08/31] crypto: qat - add packed to init admin structures Giovanni Cabiddu
2020-10-12 20:38 ` [PATCH 09/31] crypto: qat - rename ME in AE Giovanni Cabiddu
2020-10-12 20:38 ` [PATCH 10/31] crypto: qat - change admin sequence Giovanni Cabiddu
2020-10-12 20:38 ` [PATCH 11/31] crypto: qat - use admin mask to send fw constants Giovanni Cabiddu
2020-10-12 20:38 ` [PATCH 12/31] crypto: qat - update constants table Giovanni Cabiddu
2020-10-12 20:38 ` [PATCH 13/31] crypto: qat - remove writes into WQCFG Giovanni Cabiddu
2020-10-12 20:38 ` [PATCH 14/31] crypto: qat - remove unused macros in arbiter module Giovanni Cabiddu
2020-10-12 20:38 ` [PATCH 15/31] crypto: qat - abstract arbiter access Giovanni Cabiddu
2020-10-12 20:38 ` [PATCH 16/31] crypto: qat - add support for capability detection Giovanni Cabiddu
2020-10-12 20:38 ` [PATCH 17/31] crypto: qat - register crypto instances based on capability Giovanni Cabiddu
2020-10-12 20:38 ` [PATCH 18/31] crypto: qat - enable ring after pair is programmed Giovanni Cabiddu
2020-10-12 20:38 ` [PATCH 19/31] crypto: qat - abstract build ring base Giovanni Cabiddu
2020-10-12 20:38 ` [PATCH 20/31] crypto: qat - replace constant masks with GENMASK Giovanni Cabiddu
2020-10-12 20:38 ` [PATCH 21/31] crypto: qat - use BIT_ULL() - 1 pattern for masks Giovanni Cabiddu
2020-10-12 20:38 ` [PATCH 22/31] crypto: qat - abstract writes to arbiter enable Giovanni Cabiddu
2020-10-12 20:38 ` [PATCH 23/31] crypto: qat - remove hardcoded bank irq clear flag mask Giovanni Cabiddu
2020-10-12 20:38 ` [PATCH 24/31] crypto: qat - call functions in adf_sriov if available Giovanni Cabiddu
2020-10-12 20:38 ` [PATCH 25/31] crypto: qat - remove unnecessary void* casts Giovanni Cabiddu
2020-10-12 20:38 ` [PATCH 26/31] crypto: qat - change return value in adf_cfg_add_key_value_param() Giovanni Cabiddu
2020-10-12 20:38 ` [PATCH 27/31] crypto: qat - change return value in adf_cfg_key_val_get() Giovanni Cabiddu
2020-10-12 20:38 ` [PATCH 28/31] crypto: qat - refactor qat_crypto_create_instances() Giovanni Cabiddu
2020-10-12 20:38 ` [PATCH 29/31] crypto: qat - refactor qat_crypto_dev_config() Giovanni Cabiddu
2020-10-12 20:38 ` [PATCH 30/31] crypto: qat - allow for instances in different banks Giovanni Cabiddu
2020-10-12 20:38 ` [PATCH 31/31] crypto: qat - extend ae_mask Giovanni Cabiddu
2020-10-30 6:49 ` [PATCH 00/31] crypto: qat - rework in preparation for qat_4xxx driver Herbert Xu
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