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From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v4 21/61] drm/i915: Pass ww ctx to intel_pin_to_display_plane
Date: Fri, 16 Oct 2020 12:44:04 +0200	[thread overview]
Message-ID: <20201016104444.1492028-22-maarten.lankhorst@linux.intel.com> (raw)
In-Reply-To: <20201016104444.1492028-1-maarten.lankhorst@linux.intel.com>

Instead of multiple lockings, lock the object once,
and perform the ww dance around attach_phys and pin_pages.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 69 ++++++++++++-------
 drivers/gpu/drm/i915/display/intel_display.h  |  2 +-
 drivers/gpu/drm/i915/display/intel_fbdev.c    |  2 +-
 drivers/gpu/drm/i915/display/intel_overlay.c  | 34 +++++++--
 drivers/gpu/drm/i915/gem/i915_gem_domain.c    | 30 ++------
 drivers/gpu/drm/i915/gem/i915_gem_object.h    |  1 +
 drivers/gpu/drm/i915/gem/i915_gem_phys.c      | 10 +--
 .../drm/i915/gem/selftests/i915_gem_phys.c    |  2 +
 8 files changed, 86 insertions(+), 64 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5690e2ae2366..3bd8ed4e8ff4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2232,6 +2232,7 @@ static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
 
 struct i915_vma *
 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
+			   bool phys_cursor,
 			   const struct i915_ggtt_view *view,
 			   bool uses_fence,
 			   unsigned long *out_flags)
@@ -2240,14 +2241,19 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 	intel_wakeref_t wakeref;
+	struct i915_gem_ww_ctx ww;
 	struct i915_vma *vma;
 	unsigned int pinctl;
 	u32 alignment;
+	int ret;
 
 	if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj)))
 		return ERR_PTR(-EINVAL);
 
-	alignment = intel_surf_alignment(fb, 0);
+	if (phys_cursor)
+		alignment = intel_cursor_alignment(dev_priv);
+	else
+		alignment = intel_surf_alignment(fb, 0);
 	if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment)))
 		return ERR_PTR(-EINVAL);
 
@@ -2282,14 +2288,26 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
 	if (HAS_GMCH(dev_priv))
 		pinctl |= PIN_MAPPABLE;
 
-	vma = i915_gem_object_pin_to_display_plane(obj,
-						   alignment, view, pinctl);
-	if (IS_ERR(vma))
+	i915_gem_ww_ctx_init(&ww, true);
+retry:
+	ret = i915_gem_object_lock(obj, &ww);
+	if (!ret && phys_cursor)
+		ret = i915_gem_object_attach_phys(obj, alignment);
+	if (!ret)
+		ret = i915_gem_object_pin_pages(obj);
+	if (ret)
 		goto err;
 
-	if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
-		int ret;
+	if (!ret) {
+		vma = i915_gem_object_pin_to_display_plane(obj, &ww, alignment,
+							   view, pinctl);
+		if (IS_ERR(vma)) {
+			ret = PTR_ERR(vma);
+			goto err_unpin;
+		}
+	}
 
+	if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
 		/*
 		 * Install a fence for tiled scan-out. Pre-i965 always needs a
 		 * fence, whereas 965+ only requires a fence if using
@@ -2310,16 +2328,28 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
 		ret = i915_vma_pin_fence(vma);
 		if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
 			i915_gem_object_unpin_from_display_plane(vma);
-			vma = ERR_PTR(ret);
-			goto err;
+			goto err_unpin;
 		}
+		ret = 0;
 
-		if (ret == 0 && vma->fence)
+		if (vma->fence)
 			*out_flags |= PLANE_HAS_FENCE;
 	}
 
 	i915_vma_get(vma);
+
+err_unpin:
+	i915_gem_object_unpin_pages(obj);
 err:
+	if (ret == -EDEADLK) {
+		ret = i915_gem_ww_ctx_backoff(&ww);
+		if (!ret)
+			goto retry;
+	}
+	i915_gem_ww_ctx_fini(&ww);
+	if (ret)
+		vma = ERR_PTR(ret);
+
 	atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
 	intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
 	return vma;
@@ -16144,19 +16174,11 @@ static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	struct drm_framebuffer *fb = plane_state->hw.fb;
 	struct i915_vma *vma;
+	bool phys_cursor =
+		plane->id == PLANE_CURSOR &&
+		INTEL_INFO(dev_priv)->display.cursor_needs_physical;
 
-	if (plane->id == PLANE_CURSOR &&
-	    INTEL_INFO(dev_priv)->display.cursor_needs_physical) {
-		struct drm_i915_gem_object *obj = intel_fb_obj(fb);
-		const int align = intel_cursor_alignment(dev_priv);
-		int err;
-
-		err = i915_gem_object_attach_phys(obj, align);
-		if (err)
-			return err;
-	}
-
-	vma = intel_pin_and_fence_fb_obj(fb,
+	vma = intel_pin_and_fence_fb_obj(fb, phys_cursor,
 					 &plane_state->view,
 					 intel_plane_uses_fence(plane_state),
 					 &plane_state->flags);
@@ -16252,13 +16274,8 @@ intel_prepare_plane_fb(struct drm_plane *_plane,
 	if (!obj)
 		return 0;
 
-	ret = i915_gem_object_pin_pages(obj);
-	if (ret)
-		return ret;
 
 	ret = intel_plane_pin_fb(new_plane_state);
-
-	i915_gem_object_unpin_pages(obj);
 	if (ret)
 		return ret;
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index d10b7c8cde3f..03058d69d15d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -551,7 +551,7 @@ void intel_release_load_detect_pipe(struct drm_connector *connector,
 				    struct intel_load_detect_pipe *old,
 				    struct drm_modeset_acquire_ctx *ctx);
 struct i915_vma *
-intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
+intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, bool phys_cursor,
 			   const struct i915_ggtt_view *view,
 			   bool uses_fence,
 			   unsigned long *out_flags);
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 842c04e63214..bdf44e923cc0 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -211,7 +211,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
 	 * This also validates that any existing fb inherited from the
 	 * BIOS is suitable for own access.
 	 */
-	vma = intel_pin_and_fence_fb_obj(&ifbdev->fb->base,
+	vma = intel_pin_and_fence_fb_obj(&ifbdev->fb->base, false,
 					 &view, false, &flags);
 	if (IS_ERR(vma)) {
 		ret = PTR_ERR(vma);
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
index 52b4f6193b4c..9cf634cc7084 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -755,6 +755,32 @@ static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params)
 	return cmd;
 }
 
+static struct i915_vma *intel_overlay_pin_fb(struct drm_i915_gem_object *new_bo)
+{
+	struct i915_gem_ww_ctx ww;
+	struct i915_vma *vma;
+	int ret;
+
+	i915_gem_ww_ctx_init(&ww, true);
+retry:
+	ret = i915_gem_object_lock(new_bo, &ww);
+	if (!ret) {
+		vma = i915_gem_object_pin_to_display_plane(new_bo, &ww, 0,
+							   NULL, PIN_MAPPABLE);
+		ret = PTR_ERR_OR_ZERO(vma);
+	}
+	if (ret == -EDEADLK) {
+		ret = i915_gem_ww_ctx_backoff(&ww);
+		if (!ret)
+			goto retry;
+	}
+	i915_gem_ww_ctx_fini(&ww);
+	if (ret)
+		return ERR_PTR(ret);
+
+	return vma;
+}
+
 static int intel_overlay_do_put_image(struct intel_overlay *overlay,
 				      struct drm_i915_gem_object *new_bo,
 				      struct drm_intel_overlay_put_image *params)
@@ -776,12 +802,10 @@ static int intel_overlay_do_put_image(struct intel_overlay *overlay,
 
 	atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
 
-	vma = i915_gem_object_pin_to_display_plane(new_bo,
-						   0, NULL, PIN_MAPPABLE);
-	if (IS_ERR(vma)) {
-		ret = PTR_ERR(vma);
+	vma = intel_overlay_pin_fb(new_bo);
+	if (IS_ERR(vma))
 		goto out_pin_section;
-	}
+
 	i915_gem_object_flush_frontbuffer(new_bo, ORIGIN_DIRTYFB);
 
 	if (!overlay->active) {
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 43c22648b074..9adced5a6843 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -313,12 +313,12 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
  */
 struct i915_vma *
 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
+				     struct i915_gem_ww_ctx *ww,
 				     u32 alignment,
 				     const struct i915_ggtt_view *view,
 				     unsigned int flags)
 {
 	struct drm_i915_private *i915 = to_i915(obj->base.dev);
-	struct i915_gem_ww_ctx ww;
 	struct i915_vma *vma;
 	int ret;
 
@@ -326,11 +326,6 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
 	if (HAS_LMEM(i915) && !i915_gem_object_is_lmem(obj))
 		return ERR_PTR(-EINVAL);
 
-	i915_gem_ww_ctx_init(&ww, true);
-retry:
-	ret = i915_gem_object_lock(obj, &ww);
-	if (ret)
-		goto err;
 	/*
 	 * The display engine is not coherent with the LLC cache on gen6.  As
 	 * a result, we make sure that the pinning that is about to occur is
@@ -345,7 +340,7 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
 					      HAS_WT(i915) ?
 					      I915_CACHE_WT : I915_CACHE_NONE);
 	if (ret)
-		goto err;
+		return ERR_PTR(ret);
 
 	/*
 	 * As the user may map the buffer once pinned in the display plane
@@ -358,32 +353,19 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
 	vma = ERR_PTR(-ENOSPC);
 	if ((flags & PIN_MAPPABLE) == 0 &&
 	    (!view || view->type == I915_GGTT_VIEW_NORMAL))
-		vma = i915_gem_object_ggtt_pin_ww(obj, &ww, view, 0, alignment,
+		vma = i915_gem_object_ggtt_pin_ww(obj, ww, view, 0, alignment,
 						  flags | PIN_MAPPABLE |
 						  PIN_NONBLOCK);
 	if (IS_ERR(vma) && vma != ERR_PTR(-EDEADLK))
-		vma = i915_gem_object_ggtt_pin_ww(obj, &ww, view, 0,
+		vma = i915_gem_object_ggtt_pin_ww(obj, ww, view, 0,
 						  alignment, flags);
-	if (IS_ERR(vma)) {
-		ret = PTR_ERR(vma);
-		goto err;
-	}
+	if (IS_ERR(vma))
+		return vma;
 
 	vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
 
 	i915_gem_object_flush_if_display_locked(obj);
 
-err:
-	if (ret == -EDEADLK) {
-		ret = i915_gem_ww_ctx_backoff(&ww);
-		if (!ret)
-			goto retry;
-	}
-	i915_gem_ww_ctx_fini(&ww);
-
-	if (ret)
-		return ERR_PTR(ret);
-
 	return vma;
 }
 
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index b7d15a3db10e..d3086a59b5ad 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -466,6 +466,7 @@ int __must_check
 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
 struct i915_vma * __must_check
 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
+				     struct i915_gem_ww_ctx *ww,
 				     u32 alignment,
 				     const struct i915_ggtt_view *view,
 				     unsigned int flags);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_phys.c b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
index 4322e35cfe48..15d8f8d52cbe 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_phys.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
@@ -169,6 +169,8 @@ int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, int align)
 {
 	int err;
 
+	assert_object_held(obj);
+
 	if (align > obj->base.size)
 		return -EINVAL;
 
@@ -182,13 +184,9 @@ int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, int align)
 	if (err)
 		return err;
 
-	err = i915_gem_object_lock_interruptible(obj, NULL);
-	if (err)
-		return err;
-
 	err = mutex_lock_interruptible(&obj->mm.lock);
 	if (err)
-		goto err_unlock;
+		return err;
 
 	if (unlikely(!i915_gem_object_has_struct_page(obj)))
 		goto out;
@@ -219,8 +217,6 @@ int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, int align)
 
 out:
 	mutex_unlock(&obj->mm.lock);
-err_unlock:
-	i915_gem_object_unlock(obj);
 	return err;
 }
 
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c
index 0cfa082047fe..3a6ce87f8b52 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c
@@ -31,7 +31,9 @@ static int mock_phys_object(void *arg)
 		goto out_obj;
 	}
 
+	i915_gem_object_lock(obj, NULL);
 	err = i915_gem_object_attach_phys(obj, PAGE_SIZE);
+	i915_gem_object_unlock(obj);
 	if (err) {
 		pr_err("i915_gem_object_attach_phys failed, err=%d\n", err);
 		goto out_obj;
-- 
2.28.0

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  parent reply	other threads:[~2020-10-16 10:45 UTC|newest]

Thread overview: 139+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-16 10:43 [Intel-gfx] [PATCH v4 00/61] drm/i915: Remove obj->mm.lock! Maarten Lankhorst
2020-10-16 10:43 ` [Intel-gfx] [PATCH v4 01/61] drm/i915: Move cmd parser pinning to execbuffer Maarten Lankhorst
2020-11-03 13:49   ` Thomas Hellström
2020-10-16 10:43 ` [Intel-gfx] [PATCH v4 02/61] drm/i915: Add missing -EDEADLK handling to execbuf pinning Maarten Lankhorst
2020-10-20 20:18   ` Matthew Brost
2020-10-30  8:43     ` Maarten Lankhorst
2020-10-30 15:11   ` Thomas Hellström
2020-10-16 10:43 ` [Intel-gfx] [PATCH v4 03/61] drm/i915: Do not share hwsp across contexts any more, v4 Maarten Lankhorst
2020-10-16 10:59   ` [Intel-gfx] [PATCH v4] " Maarten Lankhorst
2020-10-19 12:49     ` [Intel-gfx] [PATCH] drm/i915: Do not share hwsp across contexts any more, v5 Maarten Lankhorst
2020-10-19 13:01       ` [Intel-gfx] [PATCH v5.1] " Maarten Lankhorst
2020-10-16 10:43 ` [Intel-gfx] [PATCH v4 04/61] drm/i915: Pin timeline map after first timeline pin, v3 Maarten Lankhorst
2020-10-16 12:30   ` [Intel-gfx] [PATCH v4.1] " Maarten Lankhorst
2020-10-16 14:16     ` [Intel-gfx] [PATCH v4.2] " Maarten Lankhorst
2020-10-16 10:43 ` [Intel-gfx] [PATCH v4 05/61] drm/i915: Ensure we hold the object mutex in pin correctly Maarten Lankhorst
2020-10-16 10:43 ` [Intel-gfx] [PATCH v4 06/61] drm/i915: Add gem object locking to madvise Maarten Lankhorst
2020-10-30  8:26   ` Thomas Hellström
2020-10-16 10:43 ` [Intel-gfx] [PATCH v4 07/61] drm/i915: Move HAS_STRUCT_PAGE to obj->flags Maarten Lankhorst
2020-10-30  8:31   ` Thomas Hellström
2020-10-16 10:43 ` [Intel-gfx] [PATCH v4 08/61] drm/i915: Rework struct phys attachment handling Maarten Lankhorst
2020-10-30  8:34   ` Thomas Hellström
2020-10-16 10:43 ` [Intel-gfx] [PATCH v4 09/61] drm/i915: Convert i915_gem_object_attach_phys() to ww locking Maarten Lankhorst
2020-10-30  8:38   ` Thomas Hellström (Intel)
2020-10-16 10:43 ` [Intel-gfx] [PATCH v4 10/61] drm/i915: make lockdep slightly happier about execbuf Maarten Lankhorst
2020-10-30  8:59   ` Thomas Hellström
2020-10-16 10:43 ` [Intel-gfx] [PATCH v4 11/61] drm/i915: Disable userptr pread/pwrite support Maarten Lankhorst
2020-10-30  9:03   ` Thomas Hellström
2020-10-16 10:43 ` [Intel-gfx] [PATCH v4 12/61] drm/i915: No longer allow exporting userptr through dma-buf Maarten Lankhorst
2020-10-30  9:04   ` Thomas Hellström (Intel)
2020-10-16 10:43 ` [Intel-gfx] [PATCH v4 13/61] drm/i915: Reject more ioctls for userptr Maarten Lankhorst
2020-10-30  9:22   ` Thomas Hellström (Intel)
2020-10-30  9:56     ` Maarten Lankhorst
2020-10-30 14:14       ` Thomas Hellström (Intel)
2020-10-16 10:43 ` [Intel-gfx] [PATCH v4 14/61] drm/i915: Reject UNSYNCHRONIZED " Maarten Lankhorst
2020-10-30  9:26   ` Thomas Hellström (Intel)
2020-10-30 10:10     ` Maarten Lankhorst
2020-10-30 14:15       ` Thomas Hellström (Intel)
2020-10-30 10:11     ` Maarten Lankhorst
2020-10-30 14:18       ` Thomas Hellström (Intel)
2020-11-02  8:50         ` Maarten Lankhorst
2020-10-16 10:43 ` [Intel-gfx] [PATCH v4 15/61] drm/i915: Fix userptr so we do not have to worry about obj->mm.lock, v4 Maarten Lankhorst
2020-10-19  7:30   ` Thomas Hellström (Intel)
2020-10-19  7:52     ` Thomas Hellström (Intel)
2020-10-19  8:10     ` Maarten Lankhorst
2020-10-20  6:28       ` Thomas Hellström (Intel)
2020-10-16 10:43 ` [Intel-gfx] [PATCH v4 16/61] drm/i915: Flatten obj->mm.lock Maarten Lankhorst
2020-10-30  9:36   ` Thomas Hellström (Intel)
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 17/61] drm/i915: Populate logical context during first pin Maarten Lankhorst
2020-10-30  9:42   ` Thomas Hellström
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 18/61] drm/i915: Make ring submission compatible with obj->mm.lock removal, v2 Maarten Lankhorst
2020-10-30  9:46   ` Thomas Hellström (Intel)
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 19/61] drm/i915: Handle ww locking in init_status_page Maarten Lankhorst
2020-10-30  9:48   ` Thomas Hellström (Intel)
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 20/61] drm/i915: Rework clflush to work correctly without obj->mm.lock Maarten Lankhorst
2020-10-30 15:08   ` Thomas Hellström
2020-11-02  8:48     ` Maarten Lankhorst
2020-11-02  9:22       ` Thomas Hellström
2020-11-05  7:10         ` Thomas Hellström
2020-10-16 10:44 ` Maarten Lankhorst [this message]
2020-11-03 13:54   ` [Intel-gfx] [PATCH v4 21/61] drm/i915: Pass ww ctx to intel_pin_to_display_plane Thomas Hellström
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 22/61] drm/i915: Add object locking to vm_fault_cpu Maarten Lankhorst
2020-10-30 15:14   ` Thomas Hellström
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 23/61] drm/i915: Move pinning to inside engine_wa_list_verify() Maarten Lankhorst
2020-10-30 15:17   ` Thomas Hellström
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 24/61] drm/i915: Take reservation lock around i915_vma_pin Maarten Lankhorst
2020-10-30 15:21   ` Thomas Hellström
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 25/61] drm/i915: Make intel_init_workaround_bb more compatible with ww locking Maarten Lankhorst
2020-10-30 15:23   ` Thomas Hellström
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 26/61] drm/i915: Make __engine_unpark() " Maarten Lankhorst
2020-10-16 14:08   ` [Intel-gfx] [PATCH v4.1] " Maarten Lankhorst
2020-10-30 15:25   ` [Intel-gfx] [PATCH v4 26/61] " Thomas Hellström
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 27/61] drm/i915: Take obj lock around set_domain ioctl Maarten Lankhorst
2020-11-02  9:56   ` Thomas Hellström
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 28/61] drm/i915: Defer pin calls in buffer pool until first use by caller Maarten Lankhorst
2020-11-02  9:53   ` Thomas Hellström
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 29/61] drm/i915: Fix pread/pwrite to work with new locking rules Maarten Lankhorst
2020-11-02 10:00   ` Thomas Hellström
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 30/61] drm/i915: Fix workarounds selftest, part 1 Maarten Lankhorst
2020-11-02 10:06   ` Thomas Hellström
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 31/61] drm/i915: Prepare for obj->mm.lock removal Maarten Lankhorst
2020-11-02 10:13   ` Thomas Hellström
2020-11-04 16:01     ` Maarten Lankhorst
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 32/61] drm/i915: Add igt_spinner_pin() to allow for ww locking around spinner Maarten Lankhorst
2020-11-03  8:55   ` Thomas Hellström (Intel)
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 33/61] drm/i915: Add ww locking around vm_access() Maarten Lankhorst
2020-11-03  8:56   ` Thomas Hellström (Intel)
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 34/61] drm/i915: Increase ww locking for perf Maarten Lankhorst
2020-11-03  8:58   ` Thomas Hellström (Intel)
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 35/61] drm/i915: Lock ww in ucode objects correctly Maarten Lankhorst
2020-11-03  9:00   ` Thomas Hellström (Intel)
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 36/61] drm/i915: Add ww locking to dma-buf ops Maarten Lankhorst
2020-11-03  9:02   ` Thomas Hellström (Intel)
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 37/61] drm/i915: Add missing ww lock in intel_dsb_prepare Maarten Lankhorst
2020-11-03  9:04   ` Thomas Hellström
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 38/61] drm/i915: Fix ww locking in shmem_create_from_object Maarten Lankhorst
2020-11-03  9:06   ` Thomas Hellström
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 39/61] drm/i915: Use a single page table lock for each gtt Maarten Lankhorst
2020-11-03  9:09   ` Thomas Hellström
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 40/61] drm/i915/selftests: Prepare huge_pages testcases for obj->mm.lock removal Maarten Lankhorst
2020-11-03 13:21   ` Thomas Hellström
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 41/61] drm/i915/selftests: Prepare client blit " Maarten Lankhorst
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 42/61] drm/i915/selftests: Prepare coherency tests " Maarten Lankhorst
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 43/61] drm/i915/selftests: Prepare context " Maarten Lankhorst
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 44/61] drm/i915/selftests: Prepare dma-buf " Maarten Lankhorst
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 45/61] drm/i915/selftests: Prepare execbuf " Maarten Lankhorst
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 46/61] drm/i915/selftests: Prepare mman testcases " Maarten Lankhorst
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 47/61] drm/i915/selftests: Prepare object tests " Maarten Lankhorst
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 48/61] drm/i915/selftests: Prepare object blit " Maarten Lankhorst
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 49/61] drm/i915/selftests: Prepare igt_gem_utils " Maarten Lankhorst
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 50/61] drm/i915/selftests: Prepare context selftest " Maarten Lankhorst
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 51/61] drm/i915/selftests: Prepare hangcheck " Maarten Lankhorst
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 52/61] drm/i915/selftests: Prepare execlists " Maarten Lankhorst
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 53/61] drm/i915/selftests: Prepare mocs tests " Maarten Lankhorst
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 54/61] drm/i915/selftests: Prepare ring submission " Maarten Lankhorst
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 55/61] drm/i915/selftests: Prepare timeline tests " Maarten Lankhorst
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 56/61] drm/i915/selftests: Prepare i915_request " Maarten Lankhorst
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 57/61] drm/i915/selftests: Prepare memory region " Maarten Lankhorst
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 58/61] drm/i915/selftests: Prepare cs engine " Maarten Lankhorst
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 59/61] drm/i915/selftests: Prepare gtt " Maarten Lankhorst
2020-11-03 13:27   ` Thomas Hellström
2020-11-03 13:32     ` Thomas Hellström
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 60/61] drm/i915: Finally remove obj->mm.lock Maarten Lankhorst
2020-11-03 13:31   ` Thomas Hellström
2020-10-16 10:44 ` [Intel-gfx] [PATCH v4 61/61] drm/i915: Keep userpointer bindings if seqcount is unchanged, v2 Maarten Lankhorst
2020-10-19  7:02   ` Thomas Hellström (Intel)
2020-10-16 10:49 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Remove obj->mm.lock! (rev4) Patchwork
2020-10-16 11:18 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Remove obj->mm.lock! (rev5) Patchwork
2020-10-16 12:52 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Remove obj->mm.lock! (rev6) Patchwork
2020-10-16 15:59 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Remove obj->mm.lock! (rev8) Patchwork
2020-10-16 16:00 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-10-16 16:02 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2020-10-16 16:25 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-16 18:31 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-10-19 12:53 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Remove obj->mm.lock! (rev9) Patchwork
2020-10-19 13:26 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Remove obj->mm.lock! (rev10) Patchwork
2020-10-19 13:27 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-10-19 13:29 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2020-10-19 13:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-19 15:33 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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