From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org
Cc: alistair23@gmail.com, Alistair Francis <alistair.francis@wdc.com>,
Yifei Jiang <jiangyifei@huawei.com>,
Yipeng Yin <yinyipeng1@huawei.com>
Subject: [PULL 08/18] target/riscv: Add sifive_plic vmstate
Date: Thu, 29 Oct 2020 07:13:48 -0700 [thread overview]
Message-ID: <20201029141358.3102636-9-alistair.francis@wdc.com> (raw)
In-Reply-To: <20201029141358.3102636-1-alistair.francis@wdc.com>
From: Yifei Jiang <jiangyifei@huawei.com>
Add sifive_plic vmstate for supporting sifive_plic migration.
Current vmstate framework only supports one structure parameter
as num field to describe variable length arrays, so introduce
num_enables.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201026115530.304-7-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/intc/sifive_plic.h | 1 +
hw/intc/sifive_plic.c | 26 +++++++++++++++++++++++++-
2 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/include/hw/intc/sifive_plic.h b/include/hw/intc/sifive_plic.h
index b75b1f145d..1e451a270c 100644
--- a/include/hw/intc/sifive_plic.h
+++ b/include/hw/intc/sifive_plic.h
@@ -52,6 +52,7 @@ struct SiFivePLICState {
uint32_t num_addrs;
uint32_t num_harts;
uint32_t bitfield_words;
+ uint32_t num_enables;
PLICAddr *addr_config;
uint32_t *source_priority;
uint32_t *target_priority;
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index f42fd695d8..97a1a27a9a 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -30,6 +30,7 @@
#include "hw/intc/sifive_plic.h"
#include "target/riscv/cpu.h"
#include "sysemu/sysemu.h"
+#include "migration/vmstate.h"
#define RISCV_DEBUG_PLIC 0
@@ -448,11 +449,12 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
TYPE_SIFIVE_PLIC, plic->aperture_size);
parse_hart_config(plic);
plic->bitfield_words = (plic->num_sources + 31) >> 5;
+ plic->num_enables = plic->bitfield_words * plic->num_addrs;
plic->source_priority = g_new0(uint32_t, plic->num_sources);
plic->target_priority = g_new(uint32_t, plic->num_addrs);
plic->pending = g_new0(uint32_t, plic->bitfield_words);
plic->claimed = g_new0(uint32_t, plic->bitfield_words);
- plic->enable = g_new0(uint32_t, plic->bitfield_words * plic->num_addrs);
+ plic->enable = g_new0(uint32_t, plic->num_enables);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
@@ -472,12 +474,34 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
msi_nonbroken = true;
}
+static const VMStateDescription vmstate_sifive_plic = {
+ .name = "riscv_sifive_plic",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_VARRAY_UINT32(source_priority, SiFivePLICState,
+ num_sources, 0,
+ vmstate_info_uint32, uint32_t),
+ VMSTATE_VARRAY_UINT32(target_priority, SiFivePLICState,
+ num_addrs, 0,
+ vmstate_info_uint32, uint32_t),
+ VMSTATE_VARRAY_UINT32(pending, SiFivePLICState, bitfield_words, 0,
+ vmstate_info_uint32, uint32_t),
+ VMSTATE_VARRAY_UINT32(claimed, SiFivePLICState, bitfield_words, 0,
+ vmstate_info_uint32, uint32_t),
+ VMSTATE_VARRAY_UINT32(enable, SiFivePLICState, num_enables, 0,
+ vmstate_info_uint32, uint32_t),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static void sifive_plic_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
device_class_set_props(dc, sifive_plic_properties);
dc->realize = sifive_plic_realize;
+ dc->vmsd = &vmstate_sifive_plic;
}
static const TypeInfo sifive_plic_info = {
--
2.28.0
next prev parent reply other threads:[~2020-10-29 14:30 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-29 14:13 [PULL 00/18] riscv-to-apply queue Alistair Francis
2020-10-29 14:13 ` [PULL 01/18] hw/riscv: sifive_u: Allow passing custom DTB Alistair Francis
2020-10-29 14:13 ` [PULL 02/18] hw/riscv: virt: " Alistair Francis
2020-10-29 14:13 ` [PULL 03/18] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit Alistair Francis
2020-10-29 14:13 ` [PULL 04/18] target/riscv: Add basic vmstate description of CPU Alistair Francis
2020-10-29 14:13 ` [PULL 05/18] target/riscv: Add PMP state description Alistair Francis
2020-10-29 14:13 ` [PULL 06/18] target/riscv: Add H extension " Alistair Francis
2020-10-29 14:13 ` [PULL 07/18] target/riscv: Add V " Alistair Francis
2020-10-29 14:13 ` Alistair Francis [this message]
2020-10-29 14:13 ` [PULL 09/18] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps Alistair Francis
2020-10-29 14:13 ` [PULL 10/18] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support Alistair Francis
2020-10-29 14:13 ` [PULL 11/18] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules Alistair Francis
2020-10-29 14:13 ` [PULL 12/18] hw/misc: Add Microchip PolarFire SoC IOSCB module support Alistair Francis
2020-10-29 14:13 ` [PULL 13/18] hw/riscv: microchip_pfsoc: Connect the IOSCB module Alistair Francis
2020-10-29 14:13 ` [PULL 14/18] hw/misc: Add Microchip PolarFire SoC SYSREG module support Alistair Francis
2020-10-29 14:13 ` [PULL 15/18] hw/riscv: microchip_pfsoc: Connect the SYSREG module Alistair Francis
2020-10-29 14:13 ` [PULL 16/18] hw/riscv: microchip_pfsoc: Map the reserved memory at address 0 Alistair Francis
2020-10-29 14:13 ` [PULL 17/18] hw/riscv: microchip_pfsoc: Correct DDR memory map Alistair Francis
2020-10-29 14:13 ` [PULL 18/18] hw/riscv: microchip_pfsoc: Hook the I2C1 controller Alistair Francis
2020-11-01 14:02 ` [PULL 00/18] riscv-to-apply queue Peter Maydell
2020-11-01 16:27 ` Bin Meng
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