From: Vidya Sagar <vidyas@nvidia.com>
To: <lorenzo.pieralisi@arm.com>, <robh+dt@kernel.org>,
<bhelgaas@google.com>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>, <amanharitsh123@gmail.com>,
<dinghao.liu@zju.edu.cn>, <kw@linux.com>
Cc: <linux-pci@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <kthota@nvidia.com>,
<mmaddireddy@nvidia.com>, <vidyas@nvidia.com>,
<sagar.tv@gmail.com>
Subject: [PATCH V4 2/6] PCI: tegra: Map configuration space as nGnRnE
Date: Mon, 9 Nov 2020 22:49:33 +0530 [thread overview]
Message-ID: <20201109171937.28326-3-vidyas@nvidia.com> (raw)
In-Reply-To: <20201109171937.28326-1-vidyas@nvidia.com>
As specified in the comment for pci_remap_cfgspace() define in
arch/arm64/include/asm/io.h file, PCIe configuration space should be
mapped as nGnRnE. Hence changing to dev_pci_remap_cfgspace() from
devm_ioremap_resource() for mapping DBI space as that is nothing but
the root port's own configuration space.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V4:
* None
V3:
* None
V2:
* Changed 'Strongly Ordered' to 'nGnRnE'
drivers/pci/controller/dwc/pcie-tegra194.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index b172b1d49713..7a0c64436861 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -2108,7 +2108,9 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
}
pcie->dbi_res = dbi_res;
- pci->dbi_base = devm_ioremap_resource(dev, dbi_res);
+ pci->dbi_base = devm_pci_remap_cfgspace(dev,
+ dbi_res->start,
+ resource_size(dbi_res));
if (IS_ERR(pci->dbi_base))
return PTR_ERR(pci->dbi_base);
--
2.17.1
next prev parent reply other threads:[~2020-11-09 17:20 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-09 17:19 [PATCH V4 0/6] Enhancements to Tegra194 PCIe driver Vidya Sagar
2020-11-09 17:19 ` [PATCH V4 1/6] PCI: tegra: Fix ASPM-L1SS advertisement disable code Vidya Sagar
2020-11-26 11:33 ` Thierry Reding
2020-12-03 12:36 ` Vidya Sagar
2020-11-09 17:19 ` Vidya Sagar [this message]
2020-11-26 11:33 ` [PATCH V4 2/6] PCI: tegra: Map configuration space as nGnRnE Thierry Reding
2020-12-03 12:56 ` Vidya Sagar
2020-11-09 17:19 ` [PATCH V4 3/6] PCI: tegra: Set DesignWare IP version Vidya Sagar
2020-11-26 11:34 ` Thierry Reding
2020-11-09 17:19 ` [PATCH V4 4/6] PCI: tegra: Continue unconfig sequence even if parts fail Vidya Sagar
2020-11-26 11:34 ` Thierry Reding
2020-11-30 12:10 ` Lorenzo Pieralisi
2020-12-01 14:24 ` Thierry Reding
2020-12-01 14:44 ` Lorenzo Pieralisi
2020-11-09 17:19 ` [PATCH V4 5/6] PCI: tegra: Check return value of tegra_pcie_init_controller() Vidya Sagar
2020-11-26 11:34 ` Thierry Reding
2020-11-09 17:19 ` [PATCH V4 6/6] PCI: tegra: Disable LTSSM during L2 entry Vidya Sagar
2020-11-26 11:34 ` Thierry Reding
2020-11-25 17:57 ` [PATCH V4 0/6] Enhancements to Tegra194 PCIe driver Thierry Reding
2020-11-25 19:51 ` Vidya Sagar
2020-11-26 11:31 ` Thierry Reding
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