Re: [Intel-gfx] [v9 08/12] drm/i915/display: Implement infoframes readback for LSPCON

From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Uma Shankar <uma.shankar@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [v9 08/12] drm/i915/display: Implement infoframes readback for LSPCON
Date: Wed, 25 Nov 2020 18:46:01 +0200	[thread overview]
Message-ID: <20201125164601.GW6112@intel.com> (raw)
In-Reply-To: <20201103152834.12727-9-uma.shankar@intel.com>

On Tue, Nov 03, 2020 at 08:58:30PM +0530, Uma Shankar wrote:
> Implemented Infoframes enabled readback for LSPCON devices.
> This will help align the implementation with state readback
> infrastructure.
> 
> v2: Added proper bitmask of enabled infoframes as per Ville's
> recommendation.
> 
> v3: Added pcon specific infoframe types instead of using the HSW
> one's, as recommended by Ville.
> 
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_lspcon.c | 57 ++++++++++++++++++++-
>  drivers/gpu/drm/i915/i915_reg.h             |  2 +
>  2 files changed, 57 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
> index 0cd3e0853cbf..d83e1d220658 100644
> --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> @@ -567,11 +567,64 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
>  				  buf, ret);
>  }
>  
> +static bool _lspcon_read_avi_infoframe_enabled_mca(struct drm_dp_aux *aux)
> +{
> +	int ret;
> +	u32 val = 0;
> +	u16 reg = LSPCON_MCA_AVI_IF_CTRL;
> +
> +	ret = drm_dp_dpcd_read(aux, reg, &val, 1);
> +	if (ret < 0) {
> +		DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
> +		return false;
> +	}
> +
> +	return val & LSPCON_MCA_AVI_IF_KICKOFF;
> +}
> +
> +static bool _lspcon_read_avi_infoframe_enabled_parade(struct drm_dp_aux *aux)
> +{
> +	int ret;
> +	u32 val = 0;
> +	u16 reg = LSPCON_PARADE_AVI_IF_CTRL;
> +
> +	ret = drm_dp_dpcd_read(aux, reg, &val, 1);
> +	if (ret < 0) {
> +		DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
> +		return false;
> +	}
> +
> +	return val & LSPCON_PARADE_AVI_IF_KICKOFF;
> +}
> +
>  u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
>  			      const struct intel_crtc_state *pipe_config)
>  {
> -	/* FIXME actually read this from the hw */
> -	return 0;
> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +	struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	bool infoframes_enabled;
> +	u32 val = 0;
> +	u32 mask, tmp;
> +
> +	if (lspcon->vendor == LSPCON_VENDOR_MCA)
> +		infoframes_enabled = _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux);
> +	else
> +		infoframes_enabled = _lspcon_read_avi_infoframe_enabled_parade(&intel_dp->aux);
> +
> +	if (infoframes_enabled)
> +		val |= VIDEO_DIP_ENABLE_AVI_PCON;
> +
> +	if (lspcon->hdr_supported) {
> +		tmp = intel_de_read(dev_priv,
> +				    HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
> +		mask = VIDEO_DIP_ENABLE_GMP_PCON;
> +
> +		if (tmp & mask)
> +			val |= mask;
> +	}
> +
> +	return val;
>  }
>  
>  void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bb0656875697..465ec00afbff 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5084,6 +5084,8 @@ enum {
>  #define   VIDEO_DIP_ENABLE_VS_HSW	(1 << 8)
>  #define   VIDEO_DIP_ENABLE_GMP_HSW	(1 << 4)
>  #define   VIDEO_DIP_ENABLE_SPD_HSW	(1 << 0)
> +#define   VIDEO_DIP_ENABLE_AVI_PCON	(1 << 12)
> +#define   VIDEO_DIP_ENABLE_GMP_PCON	(1 << 4)

I meant that we should just directly use
HDMI_INFOFRAME_TYPE_AVI/etc. instead of pretending
we're talking about the video DIP bits.

>  
>  /* Panel power sequencing */
>  #define PPS_BASE			0x61200
> -- 
> 2.26.2

-- 
Ville Syrjälä
Intel
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