From: Ulrich Hecht <uli+renesas@fpond.eu>
To: linux-renesas-soc@vger.kernel.org
Cc: wsa@the-dreams.de, geert@linux-m68k.org, hoai.luu.ub@renesas.com,
Ulrich Hecht <uli+renesas@fpond.eu>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Wolfram Sang <wsa+renesas@sang-engineering.com>
Subject: [PATCH v3 01/12] pinctrl: renesas: r8a779a0: Add I2C pins, groups and functions
Date: Tue, 12 Jan 2021 17:59:18 +0100 [thread overview]
Message-ID: <20210112165929.31002-2-uli+renesas@fpond.eu> (raw)
In-Reply-To: <20210112165929.31002-1-uli+renesas@fpond.eu>
This patch adds I2C0-6 pins, groups and functions to the R8A779A0 (V3U)
SoC.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
drivers/pinctrl/renesas/pfc-r8a779a0.c | 107 +++++++++++++++++++++++++
1 file changed, 107 insertions(+)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c
index 2107189d1f1d..92ba75ca6562 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779a0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c
@@ -1233,6 +1233,69 @@ static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
};
+/* - I2C0 ------------------------------------------------------------------- */
+static const unsigned int i2c0_pins[] = {
+ /* SDA0, SCL0 */
+ RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
+};
+static const unsigned int i2c0_mux[] = {
+ SDA0_MARK, SCL0_MARK,
+};
+
+/* - I2C1 ------------------------------------------------------------------- */
+static const unsigned int i2c1_pins[] = {
+ /* SDA1, SCL1 */
+ RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
+};
+static const unsigned int i2c1_mux[] = {
+ SDA1_MARK, SCL1_MARK,
+};
+
+/* - I2C2 ------------------------------------------------------------------- */
+static const unsigned int i2c2_pins[] = {
+ /* SDA2, SCL2 */
+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6),
+};
+static const unsigned int i2c2_mux[] = {
+ SDA2_MARK, SCL2_MARK,
+};
+
+/* - I2C3 ------------------------------------------------------------------- */
+static const unsigned int i2c3_pins[] = {
+ /* SDA3, SCL3 */
+ RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 8),
+};
+static const unsigned int i2c3_mux[] = {
+ SDA3_MARK, SCL3_MARK,
+};
+
+/* - I2C4 ------------------------------------------------------------------- */
+static const unsigned int i2c4_pins[] = {
+ /* SDA4, SCL4 */
+ RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
+};
+static const unsigned int i2c4_mux[] = {
+ SDA4_MARK, SCL4_MARK,
+};
+
+/* - I2C5 ------------------------------------------------------------------- */
+static const unsigned int i2c5_pins[] = {
+ /* SDA5, SCL5 */
+ RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12),
+};
+static const unsigned int i2c5_mux[] = {
+ SDA5_MARK, SCL5_MARK,
+};
+
+/* - I2C6 ------------------------------------------------------------------- */
+static const unsigned int i2c6_pins[] = {
+ /* SDA6, SCL6 */
+ RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14),
+};
+static const unsigned int i2c6_mux[] = {
+ SDA6_MARK, SCL6_MARK,
+};
+
/* - SCIF0 ------------------------------------------------------------------ */
static const unsigned int scif0_data_pins[] = {
/* RX0, TX0 */
@@ -1342,6 +1405,14 @@ static const unsigned int scif_clk_mux[] = {
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(i2c0),
+ SH_PFC_PIN_GROUP(i2c1),
+ SH_PFC_PIN_GROUP(i2c2),
+ SH_PFC_PIN_GROUP(i2c3),
+ SH_PFC_PIN_GROUP(i2c4),
+ SH_PFC_PIN_GROUP(i2c5),
+ SH_PFC_PIN_GROUP(i2c6),
+
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_clk),
SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -1358,6 +1429,34 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scif_clk),
};
+static const char * const i2c0_groups[] = {
+ "i2c0",
+};
+
+static const char * const i2c1_groups[] = {
+ "i2c1",
+};
+
+static const char * const i2c2_groups[] = {
+ "i2c2",
+};
+
+static const char * const i2c3_groups[] = {
+ "i2c3",
+};
+
+static const char * const i2c4_groups[] = {
+ "i2c4",
+};
+
+static const char * const i2c5_groups[] = {
+ "i2c5",
+};
+
+static const char * const i2c6_groups[] = {
+ "i2c6",
+};
+
static const char * const scif0_groups[] = {
"scif0_data",
"scif0_clk",
@@ -1388,6 +1487,14 @@ static const char * const scif_clk_groups[] = {
};
static const struct sh_pfc_function pinmux_functions[] = {
+ SH_PFC_FUNCTION(i2c0),
+ SH_PFC_FUNCTION(i2c1),
+ SH_PFC_FUNCTION(i2c2),
+ SH_PFC_FUNCTION(i2c3),
+ SH_PFC_FUNCTION(i2c4),
+ SH_PFC_FUNCTION(i2c5),
+ SH_PFC_FUNCTION(i2c6),
+
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif3),
--
2.20.1
next prev parent reply other threads:[~2021-01-12 17:02 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-12 16:59 [PATCH v3 00/12] pinctrl: renesas: R8A779A0 (V3U) device support Ulrich Hecht
2021-01-12 16:59 ` Ulrich Hecht [this message]
2021-01-12 16:59 ` [PATCH v3 02/12] pinctrl: renesas: r8a779a0: Add EtherAVB pins, groups and functions Ulrich Hecht
2021-01-13 13:41 ` Geert Uytterhoeven
2021-01-12 16:59 ` [PATCH v3 03/12] pinctrl: renesas: r8a779a0: Add CANFD " Ulrich Hecht
2021-01-12 16:59 ` [PATCH v3 04/12] pinctrl: renesas: r8a779a0: Add DU pins, groups and function Ulrich Hecht
2021-01-12 16:59 ` [PATCH v3 05/12] pinctrl: renesas: r8a779a0: Add HSCIF pins, groups and functions Ulrich Hecht
2021-01-12 16:59 ` [PATCH v3 06/12] pinctrl: renesas: r8a779a0: Add INTC-EX pins, groups and function Ulrich Hecht
2021-01-12 16:59 ` [PATCH v3 07/12] pinctrl: renesas: r8a779a0: Add MMC pins, groups and functions Ulrich Hecht
2021-01-12 16:59 ` [PATCH v3 08/12] pinctrl: renesas: r8a779a0: Add MSIOF " Ulrich Hecht
2021-01-13 13:46 ` Geert Uytterhoeven
2021-01-12 16:59 ` [PATCH v3 09/12] pinctrl: renesas: r8a779a0: Add PWM " Ulrich Hecht
2021-01-12 16:59 ` [PATCH v3 10/12] pinctrl: renesas: r8a779a0: Add QSPI pins, groups, " Ulrich Hecht
2021-01-12 16:59 ` [PATCH v3 11/12] pinctrl: renesas: r8a779a0: Add TMU pins, groups " Ulrich Hecht
2021-01-12 16:59 ` [PATCH v3 12/12] pinctrl: renesas: r8a779a0: Add TPU " Ulrich Hecht
2021-01-13 13:48 ` [PATCH v3 00/12] pinctrl: renesas: R8A779A0 (V3U) device support Geert Uytterhoeven
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