From: Aditya Swarup <aditya.swarup@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [Intel-gfx] [PATCH 3/9] drm/i915/adl_s: Add power wells
Date: Tue, 26 Jan 2021 20:11:53 -0800 [thread overview]
Message-ID: <20210127041159.136409-4-aditya.swarup@intel.com> (raw)
In-Reply-To: <20210127041159.136409-1-aditya.swarup@intel.com>
From: Lucas De Marchi <lucas.demarchi@intel.com>
TGL power wells can be re-used for ADL-S with the exception of the fake
power well for TC_COLD, just like DG-1.
Bspec: 53597
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 708f0b7e0990..cccfd45a67cf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4689,7 +4689,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
* The enabling order will be from lower to higher indexed wells,
* the disabling order is reversed.
*/
- if (IS_DG1(dev_priv)) {
+ if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) {
err = set_power_wells_mask(power_domains, tgl_power_wells,
BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));
} else if (IS_ROCKETLAKE(dev_priv)) {
--
2.27.0
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next prev parent reply other threads:[~2021-01-27 4:12 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-27 4:11 [Intel-gfx] [PATCH 0/9] Final set of patches for ADLS enabling Aditya Swarup
2021-01-27 4:11 ` [Intel-gfx] [PATCH 1/9] drm/i915/adl_s: Update PHY_MISC programming Aditya Swarup
2021-01-27 4:16 ` Aditya Swarup
2021-01-27 4:11 ` [Intel-gfx] [PATCH 2/9] drm/i915/adl_s: MCHBAR memory info registers are moved Aditya Swarup
2021-01-27 15:07 ` Lucas De Marchi
2021-01-27 16:48 ` Souza, Jose
2021-01-28 5:54 ` Aditya Swarup
2021-01-27 4:11 ` Aditya Swarup [this message]
2021-01-27 4:14 ` [Intel-gfx] [PATCH 3/9] drm/i915/adl_s: Add power wells Aditya Swarup
2021-01-27 5:32 ` Matt Roper
2021-01-27 4:11 ` [Intel-gfx] [PATCH 4/9] drm/i915/adl_s: Re-use TGL GuC/HuC firmware Aditya Swarup
2021-01-27 4:11 ` [Intel-gfx] [PATCH 5/9] drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION Aditya Swarup
2021-01-27 4:11 ` [Intel-gfx] [PATCH 6/9] drm/i915/adl_s: Load DMC Aditya Swarup
2021-01-27 4:15 ` Aditya Swarup
2021-01-27 15:15 ` Lucas De Marchi
2021-01-27 4:11 ` [Intel-gfx] [PATCH 7/9] drm/i915/adl_s: Update memory bandwidth parameters Aditya Swarup
2021-01-27 5:18 ` Matt Roper
2021-01-27 4:11 ` [Intel-gfx] [PATCH 8/9] drm/i915/adl_s: Add display WAs for ADL-S Aditya Swarup
2021-01-27 5:22 ` Matt Roper
2021-01-28 5:43 ` Aditya Swarup
2021-01-29 17:26 ` Souza, Jose
2021-01-27 4:11 ` [Intel-gfx] [PATCH 9/9] drm/i915/adl_s: Add GT and CTX " Aditya Swarup
2021-01-27 5:27 ` Matt Roper
2021-01-27 4:25 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Final set of patches for ADLS enabling Patchwork
2021-01-27 4:27 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-01-27 4:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-01-27 9:45 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-01-28 5:30 [Intel-gfx] [PATCH 0/9] " Aditya Swarup
2021-01-28 5:30 ` [Intel-gfx] [PATCH 3/9] drm/i915/adl_s: Add power wells Aditya Swarup
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