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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [Intel-gfx] [PATCH v2 08/14] drm/i915: Sprinkle a few missing locks around shared DDI clock registers
Date: Thu,  4 Feb 2021 20:10:42 +0200	[thread overview]
Message-ID: <20210204181048.24202-9-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20210204181048.24202-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The current code attempts to protect the RMWs into global
clock routing registers with a mutex, but forgets to do so
in a few places. Let's remedy that.

Note that at the moment we serialize all modesets onto single
wq, so this shouldn't actually matter. But maybe one day we
wish to attempt parallel modesets again...

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 76aa7d2dba52..0b2a1e0c1b8b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3457,8 +3457,12 @@ static void cnl_ddi_disable_clock(struct intel_encoder *encoder)
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
 
+	mutex_lock(&i915->dpll.lock);
+
 	intel_de_rmw(i915, DPCLKA_CFGCR0,
 		     0, DPCLKA_CFGCR0_DDI_CLK_OFF(port));
+
+	mutex_unlock(&i915->dpll.lock);
 }
 
 static void skl_ddi_enable_clock(struct intel_encoder *encoder,
@@ -3487,8 +3491,12 @@ static void skl_ddi_disable_clock(struct intel_encoder *encoder)
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
 
+	mutex_lock(&i915->dpll.lock);
+
 	intel_de_rmw(i915, DPLL_CTRL2,
 		     0, DPLL_CTRL2_DDI_CLK_OFF(port));
+
+	mutex_unlock(&i915->dpll.lock);
 }
 
 static void hsw_ddi_enable_clock(struct intel_encoder *encoder,
-- 
2.26.2

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  parent reply	other threads:[~2021-02-04 18:11 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-04 18:10 [Intel-gfx] [PATCH v2 00/14] drm/i915: Clean up the DDI clock routing mess Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 01/14] drm/i915: Introduce .{enable, disable}_clock() encoder vfuncs Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 02/14] drm/i915: Extract hsw_ddi_{enable, disable}_clock() Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 03/14] drm/i915: Extract skl_ddi_{enable, disable}_clock() Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 04/14] drm/i195: Extract cnl_ddi_{enable, disable}_clock() Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 05/14] drm/i915: Convert DG1 over to .{enable, disable}_clock() Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 06/14] drm/i915: Extract icl+ .{enable, disable}_clock() vfuncs Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 07/14] drm/i915: Use intel_de_rmw() for DDI clock routing Ville Syrjala
2021-02-04 18:10 ` Ville Syrjala [this message]
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 09/14] drm/i915: Sprinkle WARN(!pll) into icl/dg1 .clock_enable() Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 10/14] drm/i915: Extract _cnl_ddi_{enable, disable}_clock() Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 11/14] drm/i915: Split adl-s/rkl from icl_ddi_combo_{enable, disable}_clock() Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 12/14] drm/i915: Use .disable_clock() for pll sanitation Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 13/14] drm/i915: Relocate icl_sanitize_encoder_pll_mapping() Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 14/14] drm/i915: s/dev_priv/i915/ for the remainder of DDI clock routing Ville Syrjala
2021-02-04 22:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Clean up the DDI clock routing mess (rev2) Patchwork
2021-02-04 22:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-02-04 22:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-02-05  5:47 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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