From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 49/49] hw/arm/mps2: Update old infocenter.arm.com URLs
Date: Fri, 5 Mar 2021 17:15:15 +0000 [thread overview]
Message-ID: <20210305171515.1038-50-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210305171515.1038-1-peter.maydell@linaro.org>
Update old infocenter.arm.com URLs to the equivalent developer.arm.com
ones (the old URLs should redirect, but we might as well avoid the
redirection notice, and the new URLs are pleasantly shorter).
This commit covers the links to the MPS2 board TRM, the various
Application Notes, the IoTKit and SSE-200 documents.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-25-peter.maydell@linaro.org
---
include/hw/arm/armsse.h | 4 ++--
include/hw/misc/armsse-cpuid.h | 2 +-
include/hw/misc/armsse-mhu.h | 2 +-
include/hw/misc/iotkit-secctl.h | 2 +-
include/hw/misc/iotkit-sysctl.h | 2 +-
include/hw/misc/iotkit-sysinfo.h | 2 +-
include/hw/misc/mps2-fpgaio.h | 2 +-
hw/arm/mps2-tz.c | 11 +++++------
hw/misc/armsse-cpuid.c | 2 +-
hw/misc/armsse-mhu.c | 2 +-
hw/misc/iotkit-sysctl.c | 2 +-
hw/misc/iotkit-sysinfo.c | 2 +-
hw/misc/mps2-fpgaio.c | 2 +-
hw/misc/mps2-scc.c | 2 +-
14 files changed, 19 insertions(+), 20 deletions(-)
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
index 676cd4f36b0..09284ca75cf 100644
--- a/include/hw/arm/armsse.h
+++ b/include/hw/arm/armsse.h
@@ -14,9 +14,9 @@
* hardware, which include the IoT Kit and the SSE-050, SSE-100 and
* SSE-200. Currently we model:
* - the Arm IoT Kit which is documented in
- * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
+ * https://developer.arm.com/documentation/ecm0601256/latest
* - the SSE-200 which is documented in
- * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
+ * https://developer.arm.com/documentation/101104/latest/
*
* The IoTKit contains:
* a Cortex-M33
diff --git a/include/hw/misc/armsse-cpuid.h b/include/hw/misc/armsse-cpuid.h
index a61355e5161..9c0926322cb 100644
--- a/include/hw/misc/armsse-cpuid.h
+++ b/include/hw/misc/armsse-cpuid.h
@@ -12,7 +12,7 @@
/*
* This is a model of the "CPU_IDENTITY" register block which is part of the
* Arm SSE-200 and documented in
- * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
+ * https://developer.arm.com/documentation/101104/latest/
*
* QEMU interface:
* + QOM property "CPUID": the value to use for the CPUID register
diff --git a/include/hw/misc/armsse-mhu.h b/include/hw/misc/armsse-mhu.h
index 2671b5b978b..41925ded89b 100644
--- a/include/hw/misc/armsse-mhu.h
+++ b/include/hw/misc/armsse-mhu.h
@@ -12,7 +12,7 @@
/*
* This is a model of the Message Handling Unit (MHU) which is part of the
* Arm SSE-200 and documented in
- * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
+ * https://developer.arm.com/documentation/101104/latest/
*
* QEMU interface:
* + sysbus MMIO region 0: the system information register bank
diff --git a/include/hw/misc/iotkit-secctl.h b/include/hw/misc/iotkit-secctl.h
index 54c212b515c..227d44abe49 100644
--- a/include/hw/misc/iotkit-secctl.h
+++ b/include/hw/misc/iotkit-secctl.h
@@ -11,7 +11,7 @@
/* This is a model of the security controller which is part of the
* Arm IoT Kit and documented in
- * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
+ * https://developer.arm.com/documentation/ecm0601256/latest
*
* QEMU interface:
* + sysbus MMIO region 0 is the "secure privilege control block" registers
diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysctl.h
index 2b5636b218c..2bc391138db 100644
--- a/include/hw/misc/iotkit-sysctl.h
+++ b/include/hw/misc/iotkit-sysctl.h
@@ -12,7 +12,7 @@
/*
* This is a model of the "system control element" which is part of the
* Arm IoTKit and documented in
- * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
+ * https://developer.arm.com/documentation/ecm0601256/latest
* Specifically, it implements the "system information block" and
* "system control register" blocks.
*
diff --git a/include/hw/misc/iotkit-sysinfo.h b/include/hw/misc/iotkit-sysinfo.h
index 7e620e2eafe..055771d2098 100644
--- a/include/hw/misc/iotkit-sysinfo.h
+++ b/include/hw/misc/iotkit-sysinfo.h
@@ -12,7 +12,7 @@
/*
* This is a model of the "system information block" which is part of the
* Arm IoTKit and documented in
- * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
+ * https://developer.arm.com/documentation/ecm0601256/latest
* QEMU interface:
* + QOM property "SYS_VERSION": value to use for SYS_VERSION register
* + QOM property "SYS_CONFIG": value to use for SYS_CONFIG register
diff --git a/include/hw/misc/mps2-fpgaio.h b/include/hw/misc/mps2-fpgaio.h
index 0d3c8eef56c..e04fd590b63 100644
--- a/include/hw/misc/mps2-fpgaio.h
+++ b/include/hw/misc/mps2-fpgaio.h
@@ -12,7 +12,7 @@
/* This is a model of the FPGAIO register block in the AN505
* FPGA image for the MPS2 dev board; it is documented in the
* application note:
- * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html
+ * https://developer.arm.com/documentation/dai0505/latest/
*
* QEMU interface:
* + sysbus MMIO region 0: the register bank
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index 7466e71ab76..7983dc305b7 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -23,21 +23,20 @@
* https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2
*
* Board TRM:
- * http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_06_en.pdf
+ * https://developer.arm.com/documentation/100112/latest/
* Application Note AN505:
- * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html
+ * https://developer.arm.com/documentation/dai0505/latest/
* Application Note AN521:
- * http://infocenter.arm.com/help/topic/com.arm.doc.dai0521c/index.html
+ * https://developer.arm.com/documentation/dai0521/latest/
* Application Note AN524:
* https://developer.arm.com/documentation/dai0524/latest/
*
* The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide
* (ARM ECM0601256) for the details of some of the device layout:
- * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
+ * https://developer.arm.com/documentation/ecm0601256/latest
* Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM defines
* most of the device layout:
- * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
- *
+ * https://developer.arm.com/documentation/101104/latest/
*/
#include "qemu/osdep.h"
diff --git a/hw/misc/armsse-cpuid.c b/hw/misc/armsse-cpuid.c
index d58138dc28c..e785a090519 100644
--- a/hw/misc/armsse-cpuid.c
+++ b/hw/misc/armsse-cpuid.c
@@ -12,7 +12,7 @@
/*
* This is a model of the "CPU_IDENTITY" register block which is part of the
* Arm SSE-200 and documented in
- * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
+ * https://developer.arm.com/documentation/101104/latest/
*
* It consists of one read-only CPUID register (set by QOM property), plus the
* usual ID registers.
diff --git a/hw/misc/armsse-mhu.c b/hw/misc/armsse-mhu.c
index a45d97fada8..0be7f0fc874 100644
--- a/hw/misc/armsse-mhu.c
+++ b/hw/misc/armsse-mhu.c
@@ -12,7 +12,7 @@
/*
* This is a model of the Message Handling Unit (MHU) which is part of the
* Arm SSE-200 and documented in
- * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
+ * https://developer.arm.com/documentation/101104/latest/
*/
#include "qemu/osdep.h"
diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c
index 964b48c74d9..222511c4b04 100644
--- a/hw/misc/iotkit-sysctl.c
+++ b/hw/misc/iotkit-sysctl.c
@@ -12,7 +12,7 @@
/*
* This is a model of the "system control element" which is part of the
* Arm IoTKit and documented in
- * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
+ * https://developer.arm.com/documentation/ecm0601256/latest
* Specifically, it implements the "system control register" blocks.
*/
diff --git a/hw/misc/iotkit-sysinfo.c b/hw/misc/iotkit-sysinfo.c
index b2dcfc4376c..52e70053df7 100644
--- a/hw/misc/iotkit-sysinfo.c
+++ b/hw/misc/iotkit-sysinfo.c
@@ -12,7 +12,7 @@
/*
* This is a model of the "system information block" which is part of the
* Arm IoTKit and documented in
- * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
+ * https://developer.arm.com/documentation/ecm0601256/latest
* It consists of 2 read-only version/config registers, plus the
* usual ID registers.
*/
diff --git a/hw/misc/mps2-fpgaio.c b/hw/misc/mps2-fpgaio.c
index b04fcda844c..f3db88ddcc8 100644
--- a/hw/misc/mps2-fpgaio.c
+++ b/hw/misc/mps2-fpgaio.c
@@ -12,7 +12,7 @@
/* This is a model of the "FPGA system control and I/O" block found
* in the AN505 FPGA image for the MPS2 devboard.
* It is documented in AN505:
- * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html
+ * https://developer.arm.com/documentation/dai0505/latest/
*/
#include "qemu/osdep.h"
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
index 562ace06a58..140a4b9ceba 100644
--- a/hw/misc/mps2-scc.c
+++ b/hw/misc/mps2-scc.c
@@ -13,7 +13,7 @@
* found in the FPGA images of MPS2 development boards.
*
* Documentation of it can be found in the MPS2 TRM:
- * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.100112_0100_03_en/index.html
+ * https://developer.arm.com/documentation/100112/latest/
* and also in the Application Notes documenting individual FPGA images.
*/
--
2.20.1
next prev parent reply other threads:[~2021-03-05 18:10 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-05 17:14 [PULL 00/49] target-arm queue Peter Maydell
2021-03-05 17:14 ` [PULL 01/49] sbsa-ref: remove cortex-a53 from list of supported cpus Peter Maydell
2021-03-05 17:14 ` [PULL 02/49] sbsa-ref: add 'max' to list of allowed cpus Peter Maydell
2021-03-05 17:14 ` [PULL 03/49] target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe Peter Maydell
2021-03-05 17:14 ` [PULL 04/49] target/arm: Enable FEAT_SSBS for "max" AARCH64 CPU Peter Maydell
2021-03-05 17:14 ` [PULL 05/49] target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPU Peter Maydell
2021-03-05 17:14 ` [PULL 06/49] hw/net: Add npcm7xx emc model Peter Maydell
2021-03-05 17:14 ` [PULL 07/49] hw/arm: " Peter Maydell
2021-03-05 17:14 ` [PULL 08/49] tests/qtests: Add npcm7xx emc model test Peter Maydell
2021-03-05 17:14 ` [PULL 09/49] hw/arm/xlnx-zynqmp: Remove obsolete 'has_rpu' property Peter Maydell
2021-03-05 17:14 ` [PULL 10/49] target/arm: Speed up aarch64 TBL/TBX Peter Maydell
2021-03-05 17:14 ` [PULL 11/49] hw/i2c/npcm7xx_smbus: Simplify npcm7xx_smbus_init() Peter Maydell
2021-03-05 17:14 ` [PULL 12/49] virtio-mmio: improve virtio-mmio get_dev_path alog Peter Maydell
2021-03-05 17:14 ` [PULL 13/49] target/arm: Use TCF0 and TFSRE0 for unprivileged tag checks Peter Maydell
2021-03-05 17:14 ` [PULL 14/49] target/arm: Restrict v8M IDAU to TCG Peter Maydell
2021-03-05 17:14 ` [PULL 15/49] target/arm/cpu: Update coding style to make checkpatch.pl happy Peter Maydell
2021-03-05 17:14 ` [PULL 16/49] hw/arm/musicpal: Remove dead code for non-32-bit-RGB surfaces Peter Maydell
2021-03-05 17:14 ` [PULL 17/49] hw/display/tc6393xb: Remove dead code for handling non-32bpp surfaces Peter Maydell
2021-03-05 17:14 ` [PULL 18/49] hw/display/tc6393xb: Expand out macros in template header Peter Maydell
2021-03-05 17:14 ` [PULL 19/49] hw/display/tc6393xb: Inline tc6393xb_draw_graphic32() at its callsite Peter Maydell
2021-03-05 17:14 ` [PULL 20/49] hw/display/omap_lcdc: Expand out macros in template header Peter Maydell
2021-03-05 17:14 ` [PULL 21/49] hw/display/omap_lcdc: Drop broken bigendian ifdef Peter Maydell
2021-03-05 17:14 ` [PULL 22/49] hw/display/omap_lcdc: Fix coding style issues in template header Peter Maydell
2021-03-05 17:14 ` [PULL 23/49] hw/display/omap_lcdc: Inline template header into C file Peter Maydell
2021-03-05 17:14 ` [PULL 24/49] hw/display/omap_lcdc: Delete unnecessary macro Peter Maydell
2021-03-05 17:14 ` [PULL 25/49] hw/display/tcx: Drop unnecessary code for handling BGR format outputs Peter Maydell
2021-03-05 17:14 ` [PULL 26/49] hw/arm/mps2-tz: Make SYSCLK frequency board-specific Peter Maydell
2021-03-05 17:14 ` [PULL 27/49] hw/misc/mps2-scc: Support configurable number of OSCCLK values Peter Maydell
2021-03-05 17:14 ` [PULL 28/49] hw/arm/mps2-tz: Correct the OSCCLK settings for mps2-an505 and mps2-an511 Peter Maydell
2021-03-05 17:14 ` [PULL 29/49] hw/arm/mps2-tz: Make the OSCCLK settings be configurable per-board Peter Maydell
2021-03-05 17:14 ` [PULL 30/49] hw/misc/mps2-fpgaio: Make number of LEDs configurable by board Peter Maydell
2021-03-05 17:14 ` [PULL 31/49] hw/misc/mps2-fpgaio: Support SWITCH register Peter Maydell
2021-03-05 17:14 ` [PULL 32/49] hw/arm/mps2-tz: Make FPGAIO switch and LED config per-board Peter Maydell
2021-03-05 17:14 ` [PULL 33/49] hw/arm/mps2-tz: Condition IRQ splitting on number of CPUs, not board type Peter Maydell
2021-03-05 17:15 ` [PULL 34/49] hw/arm/mps2-tz: Make number of IRQs board-specific Peter Maydell
2021-03-05 17:15 ` [PULL 35/49] hw/misc/mps2-scc: Implement CFG_REG5 and CFG_REG6 for MPS3 AN524 Peter Maydell
2021-03-05 17:15 ` [PULL 36/49] hw/arm/mps2-tz: Correct wrong interrupt numbers for DMA and SPI Peter Maydell
2021-03-05 17:15 ` [PULL 37/49] hw/arm/mps2-tz: Allow PPCPortInfo structures to specify device interrupts Peter Maydell
2021-03-05 17:15 ` [PULL 38/49] hw/arm/mps2-tz: Move device IRQ info to data structures Peter Maydell
2021-03-05 17:15 ` [PULL 39/49] hw/arm/mps2-tz: Size the uart-irq-orgate based on the number of UARTs Peter Maydell
2021-03-05 17:15 ` [PULL 40/49] hw/arm/mps2-tz: Allow boards to have different PPCInfo data Peter Maydell
2021-03-05 17:15 ` [PULL 41/49] hw/arm/mps2-tz: Make RAM arrangement board-specific Peter Maydell
2021-03-05 17:15 ` [PULL 42/49] hw/arm/mps2-tz: Set MachineClass default_ram info from RAMInfo data Peter Maydell
2021-03-05 17:15 ` [PULL 43/49] hw/arm/mps2-tz: Support ROMs as well as RAMs Peter Maydell
2021-03-05 17:15 ` [PULL 44/49] hw/arm/mps2-tz: Get armv7m_load_kernel() size argument from RAMInfo Peter Maydell
2021-03-05 17:15 ` [PULL 45/49] hw/arm/mps2-tz: Add new mps3-an524 board Peter Maydell
2021-03-05 17:15 ` [PULL 46/49] hw/arm/mps2-tz: Stub out USB controller for mps3-an524 Peter Maydell
2021-03-05 17:15 ` [PULL 47/49] hw/arm/mps2-tz: Provide PL031 RTC on mps3-an524 Peter Maydell
2021-03-05 17:15 ` [PULL 48/49] docs/system/arm/mps2.rst: Document the new mps3-an524 board Peter Maydell
2021-03-05 17:15 ` Peter Maydell [this message]
2021-03-05 18:36 ` [PULL 00/49] target-arm queue no-reply
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