From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org, groug@kaod.org
Cc: Bin Meng <bmeng.cn@gmail.com>,
qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
David Gibson <david@gibson.dropbear.id.au>
Subject: [PULL 5/5] hw/net: fsl_etsec: Tx padding length should exclude CRC
Date: Wed, 31 Mar 2021 17:25:24 +1100 [thread overview]
Message-ID: <20210331062524.335749-6-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <20210331062524.335749-1-david@gibson.dropbear.id.au>
From: Bin Meng <bmeng.cn@gmail.com>
As the comment of tx_padding_and_crc() says: "Never add CRC in QEMU",
min_frame_len should excluce CRC, so it should be 60 instead of 64.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20210316081505.72898-1-bmeng.cn@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/net/fsl_etsec/rings.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/net/fsl_etsec/rings.c b/hw/net/fsl_etsec/rings.c
index d6be0d7d18..8f08446415 100644
--- a/hw/net/fsl_etsec/rings.c
+++ b/hw/net/fsl_etsec/rings.c
@@ -259,7 +259,7 @@ static void process_tx_bd(eTSEC *etsec,
|| etsec->regs[MACCFG2].value & MACCFG2_PADCRC) {
/* Padding and CRC (Padding implies CRC) */
- tx_padding_and_crc(etsec, 64);
+ tx_padding_and_crc(etsec, 60);
} else if (etsec->first_bd.flags & BD_TX_TC
|| etsec->regs[MACCFG2].value & MACCFG2_CRC_EN) {
--
2.30.2
next prev parent reply other threads:[~2021-03-31 6:36 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-31 6:25 [PULL 0/5] ppc-for-6.0 queue 20210331 David Gibson
2021-03-31 6:25 ` [PULL 1/5] hw/ppc: e500: Add missing #address-cells and #size-cells in the eTSEC node David Gibson
2021-03-31 6:25 ` [PULL 2/5] target/ppc/kvm: Cache timebase frequency David Gibson
2021-03-31 6:25 ` [PULL 3/5] spapr: Assert DIMM unplug state in spapr_memory_unplug() David Gibson
2021-03-31 6:25 ` [PULL 4/5] spapr: Fix typo in the patb_entry comment David Gibson
2021-03-31 6:25 ` David Gibson [this message]
2021-03-31 15:38 ` [PULL 0/5] ppc-for-6.0 queue 20210331 Peter Maydell
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