From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>, qemu-arm@nongnu.org
Subject: [PATCH v4 13/30] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness
Date: Fri, 16 Apr 2021 11:59:42 -0700 [thread overview]
Message-ID: <20210416185959.1520974-14-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org>
Adjust the interface to match what has been done to the
TCGv_i32 load/store functions.
This is less obvious, because at present the only user of
these functions, trans_VLDST_multiple, also wants to manipulate
the endianness to speed up loading multiple bytes. Thus we
retain an "internal" interface which is identical to the
current gen_aa32_{ld,st}_i64 interface.
The "new" interface will gain users as we remove the legacy
interfaces, gen_aa32_ld64 and gen_aa32_st64.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 78 +++++++++++++++++++--------------
target/arm/translate-neon.c.inc | 6 ++-
2 files changed, 49 insertions(+), 35 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 52b9ca502e..7472e98f09 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -949,6 +949,37 @@ static void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val,
tcg_temp_free(addr);
}
+static void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val,
+ TCGv_i32 a32, int index, MemOp opc)
+{
+ TCGv addr = gen_aa32_addr(s, a32, opc);
+
+ tcg_gen_qemu_ld_i64(val, addr, index, opc);
+
+ /* Not needed for user-mode BE32, where we use MO_BE instead. */
+ if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) {
+ tcg_gen_rotri_i64(val, val, 32);
+ }
+ tcg_temp_free(addr);
+}
+
+static void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val,
+ TCGv_i32 a32, int index, MemOp opc)
+{
+ TCGv addr = gen_aa32_addr(s, a32, opc);
+
+ /* Not needed for user-mode BE32, where we use MO_BE instead. */
+ if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) {
+ TCGv_i64 tmp = tcg_temp_new_i64();
+ tcg_gen_rotri_i64(tmp, val, 32);
+ tcg_gen_qemu_st_i64(tmp, addr, index, opc);
+ tcg_temp_free_i64(tmp);
+ } else {
+ tcg_gen_qemu_st_i64(val, addr, index, opc);
+ }
+ tcg_temp_free(addr);
+}
+
static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
int index, MemOp opc)
{
@@ -961,6 +992,18 @@ static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
gen_aa32_st_internal_i32(s, val, a32, index, finalize_memop(s, opc));
}
+static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
+ int index, MemOp opc)
+{
+ gen_aa32_ld_internal_i64(s, val, a32, index, finalize_memop(s, opc));
+}
+
+static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
+ int index, MemOp opc)
+{
+ gen_aa32_st_internal_i64(s, val, a32, index, finalize_memop(s, opc));
+}
+
#define DO_GEN_LD(SUFF, OPC) \
static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
TCGv_i32 a32, int index) \
@@ -975,47 +1018,16 @@ static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
gen_aa32_st_i32(s, val, a32, index, OPC); \
}
-static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
- int index, MemOp opc)
-{
- TCGv addr = gen_aa32_addr(s, a32, opc);
- tcg_gen_qemu_ld_i64(val, addr, index, opc);
-
- /* Not needed for user-mode BE32, where we use MO_BE instead. */
- if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) {
- tcg_gen_rotri_i64(val, val, 32);
- }
-
- tcg_temp_free(addr);
-}
-
static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val,
TCGv_i32 a32, int index)
{
- gen_aa32_ld_i64(s, val, a32, index, MO_Q | s->be_data);
-}
-
-static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
- int index, MemOp opc)
-{
- TCGv addr = gen_aa32_addr(s, a32, opc);
-
- /* Not needed for user-mode BE32, where we use MO_BE instead. */
- if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) {
- TCGv_i64 tmp = tcg_temp_new_i64();
- tcg_gen_rotri_i64(tmp, val, 32);
- tcg_gen_qemu_st_i64(tmp, addr, index, opc);
- tcg_temp_free_i64(tmp);
- } else {
- tcg_gen_qemu_st_i64(val, addr, index, opc);
- }
- tcg_temp_free(addr);
+ gen_aa32_ld_i64(s, val, a32, index, MO_Q);
}
static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val,
TCGv_i32 a32, int index)
{
- gen_aa32_st_i64(s, val, a32, index, MO_Q | s->be_data);
+ gen_aa32_st_i64(s, val, a32, index, MO_Q);
}
DO_GEN_LD(8u, MO_UB)
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
index c82aa1412e..18d9042130 100644
--- a/target/arm/translate-neon.c.inc
+++ b/target/arm/translate-neon.c.inc
@@ -494,11 +494,13 @@ static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a)
int tt = a->vd + reg + spacing * xs;
if (a->l) {
- gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, endian | size);
+ gen_aa32_ld_internal_i64(s, tmp64, addr, mmu_idx,
+ endian | size);
neon_store_element64(tt, n, size, tmp64);
} else {
neon_load_element64(tmp64, tt, n, size);
- gen_aa32_st_i64(s, tmp64, addr, mmu_idx, endian | size);
+ gen_aa32_st_internal_i64(s, tmp64, addr, mmu_idx,
+ endian | size);
}
tcg_gen_add_i32(addr, addr, tmp);
}
--
2.25.1
next prev parent reply other threads:[~2021-04-16 19:10 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-16 18:59 [PATCH v4 for-6.1 00/39] target/arm: enforce alignment Richard Henderson
2021-04-16 18:59 ` [PATCH v4 01/30] target/arm: Fix decode of align in VLDST_single Richard Henderson
2021-04-16 18:59 ` [PATCH v4 02/30] target/arm: Rename TBFLAG_A32, SCTLR_B Richard Henderson
2021-04-19 17:03 ` Peter Maydell
2021-04-19 18:19 ` Richard Henderson
2021-04-16 18:59 ` [PATCH v4 03/30] target/arm: Rename TBFLAG_ANY, PSTATE_SS Richard Henderson
2021-04-19 17:04 ` Peter Maydell
2021-04-16 18:59 ` [PATCH v4 04/30] target/arm: Add wrapper macros for accessing tbflags Richard Henderson
2021-04-19 17:04 ` Peter Maydell
2021-04-16 18:59 ` [PATCH v4 05/30] target/arm: Introduce CPUARMTBFlags Richard Henderson
2021-04-19 17:06 ` Peter Maydell
2021-04-16 18:59 ` [PATCH v4 06/30] target/arm: Move mode specific TB flags to tb->cs_base Richard Henderson
2021-04-19 17:08 ` Peter Maydell
2021-04-19 18:24 ` Richard Henderson
2021-04-16 18:59 ` [PATCH v4 07/30] target/arm: Move TBFLAG_AM32 bits to the top Richard Henderson
2021-04-19 17:07 ` Peter Maydell
2021-04-16 18:59 ` [PATCH v4 08/30] target/arm: Move TBFLAG_ANY bits to the bottom Richard Henderson
2021-04-19 17:04 ` Peter Maydell
2021-04-16 18:59 ` [PATCH v4 09/30] target/arm: Add ALIGN_MEM to TBFLAG_ANY Richard Henderson
2021-04-19 17:07 ` Peter Maydell
2021-04-16 18:59 ` [PATCH v4 10/30] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness Richard Henderson
2021-04-16 18:59 ` [PATCH v4 11/30] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64 Richard Henderson
2021-04-16 18:59 ` [PATCH v4 12/30] target/arm: Fix SCTLR_B test for TCGv_i64 load/store Richard Henderson
2021-04-16 18:59 ` Richard Henderson [this message]
2021-04-16 18:59 ` [PATCH v4 14/30] target/arm: Enforce word alignment for LDRD/STRD Richard Henderson
2021-04-16 18:59 ` [PATCH v4 15/30] target/arm: Enforce alignment for LDA/LDAH/STL/STLH Richard Henderson
2021-04-16 18:59 ` [PATCH v4 16/30] target/arm: Enforce alignment for LDM/STM Richard Henderson
2021-04-16 18:59 ` [PATCH v4 17/30] target/arm: Enforce alignment for RFE Richard Henderson
2021-04-16 18:59 ` [PATCH v4 18/30] target/arm: Enforce alignment for SRS Richard Henderson
2021-04-16 18:59 ` [PATCH v4 19/30] target/arm: Enforce alignment for VLDM/VSTM Richard Henderson
2021-04-16 18:59 ` [PATCH v4 20/30] target/arm: Enforce alignment for VLDR/VSTR Richard Henderson
2021-04-16 18:59 ` [PATCH v4 21/30] target/arm: Enforce alignment for VLDn (all lanes) Richard Henderson
2021-04-19 17:09 ` Peter Maydell
2021-04-16 18:59 ` [PATCH v4 22/30] target/arm: Enforce alignment for VLDn/VSTn (multiple) Richard Henderson
2021-04-16 18:59 ` [PATCH v4 23/30] target/arm: Enforce alignment for VLDn/VSTn (single) Richard Henderson
2021-04-16 18:59 ` [PATCH v4 24/30] target/arm: Use finalize_memop for aa64 gpr load/store Richard Henderson
2021-04-16 18:59 ` [PATCH v4 25/30] target/arm: Use finalize_memop for aa64 fpr load/store Richard Henderson
2021-04-16 18:59 ` [PATCH v4 26/30] target/arm: Enforce alignment for aa64 load-acq/store-rel Richard Henderson
2021-04-16 18:59 ` [PATCH v4 27/30] target/arm: Use MemOp for size + endian in aa64 vector ld/st Richard Henderson
2021-04-16 18:59 ` [PATCH v4 28/30] target/arm: Enforce alignment for aa64 vector LDn/STn (multiple) Richard Henderson
2021-04-16 18:59 ` [PATCH v4 29/30] target/arm: Enforce alignment for aa64 vector LDn/STn (single) Richard Henderson
2021-04-16 18:59 ` [PATCH v4 30/30] target/arm: Enforce alignment for sve LD1R Richard Henderson
2021-04-16 19:17 ` [PATCH v4 for-6.1 00/39] target/arm: enforce alignment Peter Maydell
2021-04-16 19:23 ` Richard Henderson
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