From: "David E. Box" <david.e.box@linux.intel.com>
To: irenic.rajneesh@gmail.com, david.e.box@linux.intel.com,
hdegoede@redhat.com, mgross@linux.intel.com,
gayatri.kammela@intel.com
Cc: platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH V2 0/9] intel_pmc_core: Add sub-state requirements and mode
Date: Fri, 16 Apr 2021 20:12:43 -0700 [thread overview]
Message-ID: <20210417031252.3020837-1-david.e.box@linux.intel.com> (raw)
- Patch 1 and 2 remove the use of the global struct pmc_dev
- Patches 3-7 add support for reading low power mode sub-state
requirements, latching sub-state status on different low power mode
events, and displaying the sub-state residency in microseconds
- Patch 8 adds missing LTR IPs for TGL
- Patch 9 adds support for ADL-P which is based on TGL
Applied on top of latest hans-review/review-hans
Patches that changed in V2:
Patch 3: Variable name change
Patch 5: Do proper cleanup after fail
Patch 7: Debugfs write function fixes
David E. Box (4):
platform/x86: intel_pmc_core: Don't use global pmcdev in quirks
platform/x86: intel_pmc_core: Remove global struct pmc_dev
platform/x86: intel_pmc_core: Add option to set/clear LPM mode
platform/x86: intel_pmc_core: Add support for Alder Lake PCH-P
Gayatri Kammela (5):
platform/x86: intel_pmc_core: Handle sub-states generically
platform/x86: intel_pmc_core: Show LPM residency in microseconds
platform/x86: intel_pmc_core: Get LPM requirements for Tiger Lake
platform/x86: intel_pmc_core: Add requirements file to debugfs
platform/x86: intel_pmc_core: Add LTR registers for Tiger Lake
drivers/platform/x86/intel_pmc_core.c | 384 +++++++++++++++++++++++---
drivers/platform/x86/intel_pmc_core.h | 47 +++-
2 files changed, 395 insertions(+), 36 deletions(-)
base-commit: 823b31517ad3196324322804ee365d5fcff704d6
--
2.25.1
next reply other threads:[~2021-04-17 3:12 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-17 3:12 David E. Box [this message]
2021-04-17 3:12 ` [PATCH V2 1/9] platform/x86: intel_pmc_core: Don't use global pmcdev in quirks David E. Box
2021-04-17 3:12 ` [PATCH V2 2/9] platform/x86: intel_pmc_core: Remove global struct pmc_dev David E. Box
2021-04-17 3:12 ` [PATCH V2 3/9] platform/x86: intel_pmc_core: Handle sub-states generically David E. Box
2021-04-17 3:12 ` [PATCH V2 4/9] platform/x86: intel_pmc_core: Show LPM residency in microseconds David E. Box
2021-04-17 3:12 ` [PATCH V2 5/9] platform/x86: intel_pmc_core: Get LPM requirements for Tiger Lake David E. Box
2021-04-17 5:55 ` kernel test robot
2021-04-17 5:55 ` kernel test robot
2021-04-17 6:25 ` kernel test robot
2021-04-17 6:25 ` kernel test robot
2021-04-17 8:52 ` Hans de Goede
2021-04-18 1:59 ` David E. Box
2021-04-17 9:00 ` Hans de Goede
2021-04-18 1:43 ` David E. Box
2021-04-17 3:12 ` [PATCH V2 6/9] platform/x86: intel_pmc_core: Add requirements file to debugfs David E. Box
2021-04-17 3:12 ` [PATCH V2 7/9] platform/x86: intel_pmc_core: Add option to set/clear LPM mode David E. Box
2021-04-17 3:12 ` [PATCH V2 8/9] platform/x86: intel_pmc_core: Add LTR registers for Tiger Lake David E. Box
2021-04-17 3:12 ` [PATCH V2 9/9] platform/x86: intel_pmc_core: Add support for Alder Lake PCH-P David E. Box
2021-04-17 9:12 ` [PATCH V2 0/9] intel_pmc_core: Add sub-state requirements and mode Hans de Goede
2021-04-19 8:47 ` Hans de Goede
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