From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org
Cc: Vijai Kumar K <vijai@behindbytes.com>,
alistair23@gmail.com, Alistair Francis <alistair.francis@wdc.com>,
qemu-devel@nongnu.org
Subject: [PULL v2 06/42] riscv: Add initial support for Shakti C machine
Date: Thu, 6 May 2021 09:22:36 +1000 [thread overview]
Message-ID: <20210505232312.4175486-7-alistair.francis@wdc.com> (raw)
In-Reply-To: <20210505232312.4175486-1-alistair.francis@wdc.com>
From: Vijai Kumar K <vijai@behindbytes.com>
Add support for emulating Shakti reference platform based on C-class
running on arty-100T board.
https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/README.rst
Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210401181457.73039-3-vijai@behindbytes.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
default-configs/devices/riscv64-softmmu.mak | 1 +
include/hw/riscv/shakti_c.h | 73 +++++++++
hw/riscv/shakti_c.c | 170 ++++++++++++++++++++
MAINTAINERS | 7 +
hw/riscv/Kconfig | 10 ++
hw/riscv/meson.build | 1 +
6 files changed, 262 insertions(+)
create mode 100644 include/hw/riscv/shakti_c.h
create mode 100644 hw/riscv/shakti_c.c
diff --git a/default-configs/devices/riscv64-softmmu.mak b/default-configs/devices/riscv64-softmmu.mak
index d5eec75f05..bc69301fa4 100644
--- a/default-configs/devices/riscv64-softmmu.mak
+++ b/default-configs/devices/riscv64-softmmu.mak
@@ -13,3 +13,4 @@ CONFIG_SIFIVE_E=y
CONFIG_SIFIVE_U=y
CONFIG_RISCV_VIRT=y
CONFIG_MICROCHIP_PFSOC=y
+CONFIG_SHAKTI_C=y
diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h
new file mode 100644
index 0000000000..8ffc2b0213
--- /dev/null
+++ b/include/hw/riscv/shakti_c.h
@@ -0,0 +1,73 @@
+/*
+ * Shakti C-class SoC emulation
+ *
+ * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_SHAKTI_H
+#define HW_SHAKTI_H
+
+#include "hw/riscv/riscv_hart.h"
+#include "hw/boards.h"
+
+#define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc"
+#define RISCV_SHAKTI_SOC(obj) \
+ OBJECT_CHECK(ShaktiCSoCState, (obj), TYPE_RISCV_SHAKTI_SOC)
+
+typedef struct ShaktiCSoCState {
+ /*< private >*/
+ DeviceState parent_obj;
+
+ /*< public >*/
+ RISCVHartArrayState cpus;
+ DeviceState *plic;
+ MemoryRegion rom;
+
+} ShaktiCSoCState;
+
+#define TYPE_RISCV_SHAKTI_MACHINE MACHINE_TYPE_NAME("shakti_c")
+#define RISCV_SHAKTI_MACHINE(obj) \
+ OBJECT_CHECK(ShaktiCMachineState, (obj), TYPE_RISCV_SHAKTI_MACHINE)
+typedef struct ShaktiCMachineState {
+ /*< private >*/
+ MachineState parent_obj;
+
+ /*< public >*/
+ ShaktiCSoCState soc;
+} ShaktiCMachineState;
+
+enum {
+ SHAKTI_C_ROM,
+ SHAKTI_C_RAM,
+ SHAKTI_C_UART,
+ SHAKTI_C_GPIO,
+ SHAKTI_C_PLIC,
+ SHAKTI_C_CLINT,
+ SHAKTI_C_I2C,
+};
+
+#define SHAKTI_C_PLIC_HART_CONFIG "MS"
+/* Including Interrupt ID 0 (no interrupt)*/
+#define SHAKTI_C_PLIC_NUM_SOURCES 28
+/* Excluding Priority 0 */
+#define SHAKTI_C_PLIC_NUM_PRIORITIES 2
+#define SHAKTI_C_PLIC_PRIORITY_BASE 0x04
+#define SHAKTI_C_PLIC_PENDING_BASE 0x1000
+#define SHAKTI_C_PLIC_ENABLE_BASE 0x2000
+#define SHAKTI_C_PLIC_ENABLE_STRIDE 0x80
+#define SHAKTI_C_PLIC_CONTEXT_BASE 0x200000
+#define SHAKTI_C_PLIC_CONTEXT_STRIDE 0x1000
+
+#endif
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
new file mode 100644
index 0000000000..c8205d3f22
--- /dev/null
+++ b/hw/riscv/shakti_c.c
@@ -0,0 +1,170 @@
+/*
+ * Shakti C-class SoC emulation
+ *
+ * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/boards.h"
+#include "hw/riscv/shakti_c.h"
+#include "qapi/error.h"
+#include "hw/intc/sifive_plic.h"
+#include "hw/intc/sifive_clint.h"
+#include "sysemu/sysemu.h"
+#include "hw/qdev-properties.h"
+#include "exec/address-spaces.h"
+#include "hw/riscv/boot.h"
+
+
+static const struct MemmapEntry {
+ hwaddr base;
+ hwaddr size;
+} shakti_c_memmap[] = {
+ [SHAKTI_C_ROM] = { 0x00001000, 0x2000 },
+ [SHAKTI_C_RAM] = { 0x80000000, 0x0 },
+ [SHAKTI_C_UART] = { 0x00011300, 0x00040 },
+ [SHAKTI_C_GPIO] = { 0x020d0000, 0x00100 },
+ [SHAKTI_C_PLIC] = { 0x0c000000, 0x20000 },
+ [SHAKTI_C_CLINT] = { 0x02000000, 0xc0000 },
+ [SHAKTI_C_I2C] = { 0x20c00000, 0x00100 },
+};
+
+static void shakti_c_machine_state_init(MachineState *mstate)
+{
+ ShaktiCMachineState *sms = RISCV_SHAKTI_MACHINE(mstate);
+ MemoryRegion *system_memory = get_system_memory();
+ MemoryRegion *main_mem = g_new(MemoryRegion, 1);
+
+ /* Allow only Shakti C CPU for this platform */
+ if (strcmp(mstate->cpu_type, TYPE_RISCV_CPU_SHAKTI_C) != 0) {
+ error_report("This board can only be used with Shakti C CPU");
+ exit(1);
+ }
+
+ /* Initialize SoC */
+ object_initialize_child(OBJECT(mstate), "soc", &sms->soc,
+ TYPE_RISCV_SHAKTI_SOC);
+ qdev_realize(DEVICE(&sms->soc), NULL, &error_abort);
+
+ /* register RAM */
+ memory_region_init_ram(main_mem, NULL, "riscv.shakti.c.ram",
+ mstate->ram_size, &error_fatal);
+ memory_region_add_subregion(system_memory,
+ shakti_c_memmap[SHAKTI_C_RAM].base,
+ main_mem);
+
+ /* ROM reset vector */
+ riscv_setup_rom_reset_vec(mstate, &sms->soc.cpus,
+ shakti_c_memmap[SHAKTI_C_RAM].base,
+ shakti_c_memmap[SHAKTI_C_ROM].base,
+ shakti_c_memmap[SHAKTI_C_ROM].size, 0, 0,
+ NULL);
+ riscv_load_firmware(mstate->firmware, shakti_c_memmap[SHAKTI_C_RAM].base,
+ NULL);
+}
+
+static void shakti_c_machine_instance_init(Object *obj)
+{
+}
+
+static void shakti_c_machine_class_init(ObjectClass *klass, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(klass);
+ mc->desc = "RISC-V Board compatible with Shakti SDK";
+ mc->init = shakti_c_machine_state_init;
+ mc->default_cpu_type = TYPE_RISCV_CPU_SHAKTI_C;
+}
+
+static const TypeInfo shakti_c_machine_type_info = {
+ .name = TYPE_RISCV_SHAKTI_MACHINE,
+ .parent = TYPE_MACHINE,
+ .class_init = shakti_c_machine_class_init,
+ .instance_init = shakti_c_machine_instance_init,
+ .instance_size = sizeof(ShaktiCMachineState),
+};
+
+static void shakti_c_machine_type_info_register(void)
+{
+ type_register_static(&shakti_c_machine_type_info);
+}
+type_init(shakti_c_machine_type_info_register)
+
+static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp)
+{
+ ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(dev);
+ MemoryRegion *system_memory = get_system_memory();
+
+ sysbus_realize(SYS_BUS_DEVICE(&sss->cpus), &error_abort);
+
+ sss->plic = sifive_plic_create(shakti_c_memmap[SHAKTI_C_PLIC].base,
+ (char *)SHAKTI_C_PLIC_HART_CONFIG, 0,
+ SHAKTI_C_PLIC_NUM_SOURCES,
+ SHAKTI_C_PLIC_NUM_PRIORITIES,
+ SHAKTI_C_PLIC_PRIORITY_BASE,
+ SHAKTI_C_PLIC_PENDING_BASE,
+ SHAKTI_C_PLIC_ENABLE_BASE,
+ SHAKTI_C_PLIC_ENABLE_STRIDE,
+ SHAKTI_C_PLIC_CONTEXT_BASE,
+ SHAKTI_C_PLIC_CONTEXT_STRIDE,
+ shakti_c_memmap[SHAKTI_C_PLIC].size);
+
+ sifive_clint_create(shakti_c_memmap[SHAKTI_C_CLINT].base,
+ shakti_c_memmap[SHAKTI_C_CLINT].size, 0, 1,
+ SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
+ SIFIVE_CLINT_TIMEBASE_FREQ, false);
+
+ /* ROM */
+ memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom",
+ shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal);
+ memory_region_add_subregion(system_memory,
+ shakti_c_memmap[SHAKTI_C_ROM].base, &sss->rom);
+}
+
+static void shakti_c_soc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ dc->realize = shakti_c_soc_state_realize;
+}
+
+static void shakti_c_soc_instance_init(Object *obj)
+{
+ ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj);
+
+ object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY);
+
+ /*
+ * CPU type is fixed and we are not supporting passing from commandline yet.
+ * So let it be in instance_init. When supported should use ms->cpu_type
+ * instead of TYPE_RISCV_CPU_SHAKTI_C
+ */
+ object_property_set_str(OBJECT(&sss->cpus), "cpu-type",
+ TYPE_RISCV_CPU_SHAKTI_C, &error_abort);
+ object_property_set_int(OBJECT(&sss->cpus), "num-harts", 1,
+ &error_abort);
+}
+
+static const TypeInfo shakti_c_type_info = {
+ .name = TYPE_RISCV_SHAKTI_SOC,
+ .parent = TYPE_DEVICE,
+ .class_init = shakti_c_soc_class_init,
+ .instance_init = shakti_c_soc_instance_init,
+ .instance_size = sizeof(ShaktiCSoCState),
+};
+
+static void shakti_c_type_info_register(void)
+{
+ type_register_static(&shakti_c_type_info);
+}
+type_init(shakti_c_type_info_register)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6c5b5693a8..1b0386d25c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1394,6 +1394,13 @@ F: include/hw/misc/mchp_pfsoc_dmc.h
F: include/hw/misc/mchp_pfsoc_ioscb.h
F: include/hw/misc/mchp_pfsoc_sysreg.h
+Shakti C class SoC
+M: Vijai Kumar K <vijai@behindbytes.com>
+L: qemu-riscv@nongnu.org
+S: Supported
+F: hw/riscv/shakti_c.c
+F: include/hw/riscv/shakti_c.h
+
SiFive Machines
M: Alistair Francis <Alistair.Francis@wdc.com>
M: Bin Meng <bin.meng@windriver.com>
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 1de18cdcf1..a0225716b5 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -19,6 +19,16 @@ config OPENTITAN
select IBEX
select UNIMP
+config SHAKTI
+ bool
+
+config SHAKTI_C
+ bool
+ select UNIMP
+ select SHAKTI
+ select SIFIVE_CLINT
+ select SIFIVE_PLIC
+
config RISCV_VIRT
bool
imply PCI_DEVICES
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index 275c0f7eb7..a97454661c 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -4,6 +4,7 @@ riscv_ss.add(files('numa.c'))
riscv_ss.add(files('riscv_hart.c'))
riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
+riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
--
2.31.1
next prev parent reply other threads:[~2021-05-05 23:30 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-05 23:22 [PULL v2 00/42] riscv-to-apply queue Alistair Francis
2021-05-05 23:22 ` [PULL v2 01/42] target/riscv: Remove privilege v1.9 specific CSR related code Alistair Francis
2021-05-05 23:22 ` [PULL v2 02/42] docs/system/generic-loader.rst: Fix style Alistair Francis
2021-05-05 23:22 ` [PULL v2 03/42] target/riscv: Align the data type of reset vector address Alistair Francis
2021-05-05 23:22 ` [PULL v2 04/42] hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[] Alistair Francis
2021-05-05 23:22 ` [PULL v2 05/42] target/riscv: Add Shakti C class CPU Alistair Francis
2021-05-05 23:22 ` Alistair Francis [this message]
2021-05-05 23:22 ` [PULL v2 07/42] hw/char: Add Shakti UART emulation Alistair Francis
2021-05-05 23:22 ` [PULL v2 08/42] hw/riscv: Connect Shakti UART to Shakti platform Alistair Francis
2021-05-05 23:22 ` [PULL v2 09/42] target/riscv: Convert the RISC-V exceptions to an enum Alistair Francis
2021-05-05 23:22 ` [PULL v2 10/42] target/riscv: Use the RISCVException enum for CSR predicates Alistair Francis
2021-05-05 23:22 ` [PULL v2 11/42] target/riscv: Fix 32-bit HS mode access permissions Alistair Francis
2021-05-05 23:22 ` [PULL v2 12/42] target/riscv: Use the RISCVException enum for CSR operations Alistair Francis
2021-05-05 23:22 ` [PULL v2 13/42] target/riscv: Use RISCVException enum for CSR access Alistair Francis
2021-05-05 23:22 ` [PULL v2 14/42] MAINTAINERS: Update the RISC-V CPU Maintainers Alistair Francis
2021-05-05 23:22 ` [PULL v2 15/42] hw/opentitan: Update the interrupt layout Alistair Francis
2021-05-05 23:22 ` [PULL v2 16/42] hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine Alistair Francis
2021-05-05 23:22 ` [PULL v2 17/42] riscv: don't look at SUM when accessing memory from a debugger context Alistair Francis
2021-05-05 23:22 ` [PULL v2 18/42] target/riscv: Fixup saturate subtract function Alistair Francis
2021-05-05 23:22 ` [PULL v2 19/42] docs: Add documentation for shakti_c machine Alistair Francis
2021-05-05 23:22 ` [PULL v2 20/42] target/riscv: Fix the PMP is locked check when using TOR Alistair Francis
2021-05-05 23:22 ` [PULL v2 21/42] target/riscv: Define ePMP mseccfg Alistair Francis
2021-05-05 23:22 ` [PULL v2 22/42] target/riscv: Add the ePMP feature Alistair Francis
2021-05-05 23:22 ` [PULL v2 23/42] target/riscv: Add ePMP CSR access functions Alistair Francis
2021-05-05 23:22 ` [PULL v2 24/42] target/riscv: Implementation of enhanced PMP (ePMP) Alistair Francis
2021-05-05 23:22 ` [PULL v2 25/42] target/riscv: Add a config option for ePMP Alistair Francis
2021-05-05 23:22 ` [PULL v2 26/42] target/riscv/pmp: Remove outdated comment Alistair Francis
2021-05-05 23:22 ` [PULL v2 27/42] target/riscv: Add ePMP support for the Ibex CPU Alistair Francis
2021-05-05 23:22 ` [PULL v2 28/42] target/riscv: fix vrgather macro index variable type bug Alistair Francis
2021-05-05 23:22 ` [PULL v2 29/42] target/riscv: fix exception index on instruction access fault Alistair Francis
2021-05-05 23:23 ` [PULL v2 30/42] hw/riscv: Fix OT IBEX reset vector Alistair Francis
2021-05-05 23:23 ` [PULL v2 31/42] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions Alistair Francis
2021-05-05 23:23 ` [PULL v2 32/42] target/riscv: fix a typo with interrupt names Alistair Francis
2021-05-05 23:23 ` [PULL v2 33/42] target/riscv: Remove the hardcoded RVXLEN macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 34/42] target/riscv: Remove the hardcoded SSTATUS_SD macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 35/42] target/riscv: Remove the hardcoded HGATP_MODE macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 36/42] target/riscv: Remove the hardcoded MSTATUS_SD macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 37/42] target/riscv: Remove the hardcoded SATP_MODE macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 38/42] target/riscv: Remove the unused HSTATUS_WPRI macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 39/42] target/riscv: Remove an unused CASE_OP_32_64 macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 40/42] target/riscv: Consolidate RV32/64 32-bit instructions Alistair Francis
2021-05-05 23:23 ` [PULL v2 41/42] target/riscv: Consolidate RV32/64 16-bit instructions Alistair Francis
2021-05-05 23:23 ` [PULL v2 42/42] target/riscv: Fix the RV64H decode comment Alistair Francis
2021-05-11 8:29 ` [PULL v2 00/42] riscv-to-apply queue Peter Maydell
2021-05-11 10:17 ` Alistair Francis
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