From: Roger Pau Monne <roger.pau@citrix.com>
To: <xen-devel@lists.xenproject.org>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>,
Roger Pau Monne <roger.pau@citrix.com>,
Ian Jackson <iwj@xenproject.org>, Wei Liu <wl@xen.org>
Subject: [PATCH v4 06/10] libs/guest: introduce helper set cpu topology in cpu policy
Date: Fri, 7 May 2021 13:04:18 +0200 [thread overview]
Message-ID: <20210507110422.24608-7-roger.pau@citrix.com> (raw)
In-Reply-To: <20210507110422.24608-1-roger.pau@citrix.com>
This logic is pulled out from xc_cpuid_apply_policy and placed into a
separate helper. Note the legacy part of the introduced function, as
long term Xen will require a proper topology setter function capable
of expressing a more diverse set of topologies.
No functional change intended.
Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
---
- s/xc_cpu_policy_topology/xc_cpu_policy_legacy_topology/
---
tools/include/xenguest.h | 4 +
tools/libs/guest/xg_cpuid_x86.c | 182 +++++++++++++++++---------------
2 files changed, 103 insertions(+), 83 deletions(-)
diff --git a/tools/include/xenguest.h b/tools/include/xenguest.h
index 576e976d069..6fe01ae292b 100644
--- a/tools/include/xenguest.h
+++ b/tools/include/xenguest.h
@@ -758,6 +758,10 @@ bool xc_cpu_policy_is_compatible(xc_interface *xch, xc_cpu_policy_t *host,
int xc_cpu_policy_make_compat_4_12(xc_interface *xch, xc_cpu_policy_t *policy,
bool hvm);
+/* Setup the legacy policy topology. */
+int xc_cpu_policy_legacy_topology(xc_interface *xch, xc_cpu_policy_t *policy,
+ bool hvm);
+
int xc_get_cpu_levelling_caps(xc_interface *xch, uint32_t *caps);
int xc_get_cpu_featureset(xc_interface *xch, uint32_t index,
uint32_t *nr_features, uint32_t *featureset);
diff --git a/tools/libs/guest/xg_cpuid_x86.c b/tools/libs/guest/xg_cpuid_x86.c
index fccbc54a400..2c89c59cccb 100644
--- a/tools/libs/guest/xg_cpuid_x86.c
+++ b/tools/libs/guest/xg_cpuid_x86.c
@@ -438,13 +438,11 @@ int xc_cpuid_apply_policy(xc_interface *xch, uint32_t domid, bool restore,
{
int rc;
xc_dominfo_t di;
- unsigned int i, nr_leaves, nr_msrs;
+ unsigned int nr_leaves, nr_msrs;
xen_cpuid_leaf_t *leaves = NULL;
struct cpuid_policy *p = NULL;
struct xc_cpu_policy policy = { };
uint32_t err_leaf = -1, err_subleaf = -1, err_msr = -1;
- uint32_t host_featureset[FEATURESET_NR_ENTRIES] = {};
- uint32_t len = ARRAY_SIZE(host_featureset);
if ( xc_domain_getinfo(xch, domid, 1, &di) != 1 ||
di.domid != domid )
@@ -467,22 +465,6 @@ int xc_cpuid_apply_policy(xc_interface *xch, uint32_t domid, bool restore,
(p = calloc(1, sizeof(*p))) == NULL )
goto out;
- /* Get the host policy. */
- rc = xc_get_cpu_featureset(xch, XEN_SYSCTL_cpu_featureset_host,
- &len, host_featureset);
- if ( rc )
- {
- /* Tolerate "buffer too small", as we've got the bits we need. */
- if ( errno == ENOBUFS )
- rc = 0;
- else
- {
- PERROR("Failed to obtain host featureset");
- rc = -errno;
- goto out;
- }
- }
-
/* Get the domain's default policy. */
nr_msrs = 0;
rc = get_system_cpu_policy(xch, di.hvm ? XEN_SYSCTL_cpu_policy_hvm_default
@@ -566,70 +548,11 @@ int xc_cpuid_apply_policy(xc_interface *xch, uint32_t domid, bool restore,
}
}
- if ( !di.hvm )
- {
- /*
- * On hardware without CPUID Faulting, PV guests see real topology.
- * As a consequence, they also need to see the host htt/cmp fields.
- */
- p->basic.htt = test_bit(X86_FEATURE_HTT, host_featureset);
- p->extd.cmp_legacy = test_bit(X86_FEATURE_CMP_LEGACY, host_featureset);
- }
- else
- {
- /*
- * Topology for HVM guests is entirely controlled by Xen. For now, we
- * hardcode APIC_ID = vcpu_id * 2 to give the illusion of no SMT.
- */
- p->basic.htt = true;
- p->extd.cmp_legacy = false;
-
- /*
- * Leaf 1 EBX[23:16] is Maximum Logical Processors Per Package.
- * Update to reflect vLAPIC_ID = vCPU_ID * 2, but make sure to avoid
- * overflow.
- */
- if ( !(p->basic.lppp & 0x80) )
- p->basic.lppp *= 2;
-
- switch ( p->x86_vendor )
- {
- case X86_VENDOR_INTEL:
- for ( i = 0; (p->cache.subleaf[i].type &&
- i < ARRAY_SIZE(p->cache.raw)); ++i )
- {
- p->cache.subleaf[i].cores_per_package =
- (p->cache.subleaf[i].cores_per_package << 1) | 1;
- p->cache.subleaf[i].threads_per_cache = 0;
- }
- break;
-
- case X86_VENDOR_AMD:
- case X86_VENDOR_HYGON:
- /*
- * Leaf 0x80000008 ECX[15:12] is ApicIdCoreSize.
- * Leaf 0x80000008 ECX[7:0] is NumberOfCores (minus one).
- * Update to reflect vLAPIC_ID = vCPU_ID * 2. But avoid
- * - overflow,
- * - going out of sync with leaf 1 EBX[23:16],
- * - incrementing ApicIdCoreSize when it's zero (which changes the
- * meaning of bits 7:0).
- *
- * UPDATE: I addition to avoiding overflow, some
- * proprietary operating systems have trouble with
- * apic_id_size values greater than 7. Limit the value to
- * 7 for now.
- */
- if ( p->extd.nc < 0x7f )
- {
- if ( p->extd.apic_id_size != 0 && p->extd.apic_id_size < 0x7 )
- p->extd.apic_id_size++;
-
- p->extd.nc = (p->extd.nc << 1) | 1;
- }
- break;
- }
- }
+ policy.cpuid = *p;
+ rc = xc_cpu_policy_legacy_topology(xch, &policy, di.hvm);
+ if ( rc )
+ goto out;
+ *p = policy.cpuid;
rc = x86_cpuid_copy_to_buffer(p, leaves, &nr_leaves);
if ( rc )
@@ -949,3 +872,96 @@ int xc_cpu_policy_make_compat_4_12(xc_interface *xch, xc_cpu_policy_t *policy,
xc_cpu_policy_destroy(host);
return rc;
}
+
+int xc_cpu_policy_legacy_topology(xc_interface *xch, xc_cpu_policy_t *policy,
+ bool hvm)
+{
+ if ( !hvm )
+ {
+ xc_cpu_policy_t *host;
+ int rc;
+
+ host = xc_cpu_policy_init();
+ if ( !host )
+ {
+ errno = ENOMEM;
+ return -1;
+ }
+
+ rc = xc_cpu_policy_get_system(xch, XEN_SYSCTL_cpu_policy_host, host);
+ if ( rc )
+ {
+ ERROR("Failed to get host policy");
+ xc_cpu_policy_destroy(host);
+ return rc;
+ }
+
+
+ /*
+ * On hardware without CPUID Faulting, PV guests see real topology.
+ * As a consequence, they also need to see the host htt/cmp fields.
+ */
+ policy->cpuid.basic.htt = host->cpuid.basic.htt;
+ policy->cpuid.extd.cmp_legacy = host->cpuid.extd.cmp_legacy;
+ }
+ else
+ {
+ unsigned int i;
+
+ /*
+ * Topology for HVM guests is entirely controlled by Xen. For now, we
+ * hardcode APIC_ID = vcpu_id * 2 to give the illusion of no SMT.
+ */
+ policy->cpuid.basic.htt = true;
+ policy->cpuid.extd.cmp_legacy = false;
+
+ /*
+ * Leaf 1 EBX[23:16] is Maximum Logical Processors Per Package.
+ * Update to reflect vLAPIC_ID = vCPU_ID * 2, but make sure to avoid
+ * overflow.
+ */
+ if ( !(policy->cpuid.basic.lppp & 0x80) )
+ policy->cpuid.basic.lppp *= 2;
+
+ switch ( policy->cpuid.x86_vendor )
+ {
+ case X86_VENDOR_INTEL:
+ for ( i = 0; (policy->cpuid.cache.subleaf[i].type &&
+ i < ARRAY_SIZE(policy->cpuid.cache.raw)); ++i )
+ {
+ policy->cpuid.cache.subleaf[i].cores_per_package =
+ (policy->cpuid.cache.subleaf[i].cores_per_package << 1) | 1;
+ policy->cpuid.cache.subleaf[i].threads_per_cache = 0;
+ }
+ break;
+
+ case X86_VENDOR_AMD:
+ case X86_VENDOR_HYGON:
+ /*
+ * Leaf 0x80000008 ECX[15:12] is ApicIdCoreSize.
+ * Leaf 0x80000008 ECX[7:0] is NumberOfCores (minus one).
+ * Update to reflect vLAPIC_ID = vCPU_ID * 2. But avoid
+ * - overflow,
+ * - going out of sync with leaf 1 EBX[23:16],
+ * - incrementing ApicIdCoreSize when it's zero (which changes the
+ * meaning of bits 7:0).
+ *
+ * UPDATE: I addition to avoiding overflow, some
+ * proprietary operating systems have trouble with
+ * apic_id_size values greater than 7. Limit the value to
+ * 7 for now.
+ */
+ if ( policy->cpuid.extd.nc < 0x7f )
+ {
+ if ( policy->cpuid.extd.apic_id_size != 0 &&
+ policy->cpuid.extd.apic_id_size < 0x7 )
+ policy->cpuid.extd.apic_id_size++;
+
+ policy->cpuid.extd.nc = (policy->cpuid.extd.nc << 1) | 1;
+ }
+ break;
+ }
+ }
+
+ return 0;
+}
--
2.31.1
next prev parent reply other threads:[~2021-05-07 11:07 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-07 11:04 [PATCH v4 00/10] libs/guest: new CPUID/MSR interface Roger Pau Monne
2021-05-07 11:04 ` [PATCH v4 01/10] libx86: introduce helper to fetch cpuid leaf Roger Pau Monne
2021-05-07 11:04 ` [PATCH v4 02/10] libs/guest: allow fetching a specific CPUID leaf from a cpu policy Roger Pau Monne
2021-05-07 11:04 ` [PATCH v4 03/10] libx86: introduce helper to fetch msr entry Roger Pau Monne
2021-05-17 15:43 ` Jan Beulich
2021-05-18 10:50 ` Roger Pau Monné
2021-05-18 11:29 ` Jan Beulich
2021-05-07 11:04 ` [PATCH v4 04/10] libs/guest: allow fetching a specific MSR entry from a cpu policy Roger Pau Monne
2021-05-07 11:04 ` [PATCH v4 05/10] libs/guest: make a cpu policy compatible with older Xen versions Roger Pau Monne
2021-05-07 11:04 ` Roger Pau Monne [this message]
2021-05-07 11:04 ` [PATCH v4 07/10] libs/guest: rework xc_cpuid_xend_policy Roger Pau Monne
2021-05-07 11:04 ` [PATCH v4 08/10] libs/guest: apply a featureset into a cpu policy Roger Pau Monne
2021-05-07 11:04 ` [PATCH v4 09/10] libs/{light,guest}: implement xc_cpuid_apply_policy in libxl Roger Pau Monne
2021-05-14 9:36 ` Roger Pau Monné
2021-05-07 11:04 ` [PATCH v4 10/10] libs/guest: (re)move xc_cpu_policy_apply_cpuid Roger Pau Monne
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210507110422.24608-7-roger.pau@citrix.com \
--to=roger.pau@citrix.com \
--cc=andrew.cooper3@citrix.com \
--cc=iwj@xenproject.org \
--cc=wl@xen.org \
--cc=xen-devel@lists.xenproject.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.