From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [CI 1/7] drm/i915/xelpd: Handle proper AUX interrupt bits
Date: Tue, 11 May 2021 21:21:38 -0700 [thread overview]
Message-ID: <20210512042144.2089071-2-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20210512042144.2089071-1-matthew.d.roper@intel.com>
XE_LPD has new AUX interrupt bits for DDI-D and DDI-E that take the
spots that were used by TC5/TC6 on Display12 platforms.
While we're at it, let's convert the bit definitions for all TGL+ aux
bits over to the modern REG_BIT() notation.
v2:
- Maintain bit order rather than logical order. (Lucas)
- Convert surrounding code to REG_BIT() notation. (Lucas)
Bspec: 50064
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 12 +++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 20 +++++++++++---------
2 files changed, 22 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f6967a93ec7a..26a5474bb145 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2270,7 +2270,17 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
{
u32 mask;
- if (DISPLAY_VER(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 13)
+ return TGL_DE_PORT_AUX_DDIA |
+ TGL_DE_PORT_AUX_DDIB |
+ TGL_DE_PORT_AUX_DDIC |
+ XELPD_DE_PORT_AUX_DDID |
+ XELPD_DE_PORT_AUX_DDIE |
+ TGL_DE_PORT_AUX_USBC1 |
+ TGL_DE_PORT_AUX_USBC2 |
+ TGL_DE_PORT_AUX_USBC3 |
+ TGL_DE_PORT_AUX_USBC4;
+ else if (DISPLAY_VER(dev_priv) >= 12)
return TGL_DE_PORT_AUX_DDIA |
TGL_DE_PORT_AUX_DDIB |
TGL_DE_PORT_AUX_DDIC |
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 846fa927a3d8..87d7257922d0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7873,15 +7873,17 @@ enum {
#define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)
#define BXT_DE_PORT_GMBUS (1 << 1)
#define GEN8_AUX_CHANNEL_A (1 << 0)
-#define TGL_DE_PORT_AUX_USBC6 (1 << 13)
-#define TGL_DE_PORT_AUX_USBC5 (1 << 12)
-#define TGL_DE_PORT_AUX_USBC4 (1 << 11)
-#define TGL_DE_PORT_AUX_USBC3 (1 << 10)
-#define TGL_DE_PORT_AUX_USBC2 (1 << 9)
-#define TGL_DE_PORT_AUX_USBC1 (1 << 8)
-#define TGL_DE_PORT_AUX_DDIC (1 << 2)
-#define TGL_DE_PORT_AUX_DDIB (1 << 1)
-#define TGL_DE_PORT_AUX_DDIA (1 << 0)
+#define TGL_DE_PORT_AUX_USBC6 REG_BIT(13)
+#define XELPD_DE_PORT_AUX_DDIE REG_BIT(13)
+#define TGL_DE_PORT_AUX_USBC5 REG_BIT(12)
+#define XELPD_DE_PORT_AUX_DDID REG_BIT(12)
+#define TGL_DE_PORT_AUX_USBC4 REG_BIT(11)
+#define TGL_DE_PORT_AUX_USBC3 REG_BIT(10)
+#define TGL_DE_PORT_AUX_USBC2 REG_BIT(9)
+#define TGL_DE_PORT_AUX_USBC1 REG_BIT(8)
+#define TGL_DE_PORT_AUX_DDIC REG_BIT(2)
+#define TGL_DE_PORT_AUX_DDIB REG_BIT(1)
+#define TGL_DE_PORT_AUX_DDIA REG_BIT(0)
#define GEN8_DE_MISC_ISR _MMIO(0x44460)
#define GEN8_DE_MISC_IMR _MMIO(0x44464)
--
2.25.4
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next prev parent reply other threads:[~2021-05-12 4:21 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-12 4:21 [Intel-gfx] [CI 0/7] CI pass for reviewed XeLPD / ADL-P patches Matt Roper
2021-05-12 4:21 ` Matt Roper [this message]
2021-05-12 4:21 ` [Intel-gfx] [CI 2/7] drm/i915/xelpd: Define plane capabilities Matt Roper
2021-05-12 4:21 ` [Intel-gfx] [CI 3/7] drm/i915/xelpd: Add XE_LPD power wells Matt Roper
2021-05-12 4:21 ` [Intel-gfx] [CI 4/7] drm/i915/xelpd: Required bandwidth increases when VT-d is active Matt Roper
2021-05-12 4:21 ` [Intel-gfx] [CI 5/7] drm/i915/xelpd: Add Wa_14011503030 Matt Roper
2021-05-12 4:21 ` [Intel-gfx] [CI 6/7] drm/i915/adl_p: Add PCH support Matt Roper
2021-05-12 4:21 ` [Intel-gfx] [CI 7/7] drm/i915/perf: Enable OA formats for ADL_P Matt Roper
2021-05-12 4:40 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for CI pass for reviewed XeLPD / ADL-P patches Patchwork
2021-05-12 5:10 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-05-12 5:43 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for CI pass for reviewed XeLPD / ADL-P patches (rev2) Patchwork
2021-05-12 6:13 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-05-12 16:18 ` Matt Roper
2021-05-12 16:43 ` Vudum, Lakshminarayana
2021-05-12 17:45 ` Vudum, Lakshminarayana
2021-05-12 17:23 ` Patchwork
2021-05-12 17:38 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-12 19:36 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for CI pass for reviewed XeLPD / ADL-P patches (rev3) Patchwork
2021-05-12 20:05 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-12 21:47 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for CI pass for reviewed XeLPD / ADL-P patches (rev2) Patchwork
2021-05-13 0:02 ` Matt Roper
2021-05-13 1:21 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for CI pass for reviewed XeLPD / ADL-P patches (rev3) Patchwork
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