[PATCH 3/3] target/i386: Added Intercept CR0 writes check

From: Lara Lazier <laramglazier@gmail.com>
To: qemu-devel@nongnu.org
Cc: Lara Lazier <laramglazier@gmail.com>
Subject: [PATCH 3/3] target/i386: Added Intercept CR0 writes check
Date: Mon, 14 Jun 2021 12:09:02 +0200	[thread overview]
Message-ID: <20210614100902.15860-4-laramglazier@gmail.com> (raw)
In-Reply-To: <20210614100902.15860-1-laramglazier@gmail.com>

When the selective CR0 write intercept is set, all writes to bits in
CR0 other than CR0.TS or CR0.MP cause a VMEXIT.

Signed-off-by: Lara Lazier <laramglazier@gmail.com>
---
 target/i386/cpu.h                    | 2 ++
 target/i386/tcg/sysemu/misc_helper.c | 9 +++++++++
 2 files changed, 11 insertions(+)

diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 46542513cc..ff0ff97ca9 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -228,6 +228,8 @@ typedef enum X86Seg {
 #define CR0_CD_MASK  (1U << 30)
 #define CR0_PG_MASK  (1U << 31)
 
+#define INTERCEPT_SELECTIVE_CR0 (1ULL << 5)
+
 #define CR4_VME_MASK  (1U << 0)
 #define CR4_PVI_MASK  (1U << 1)
 #define CR4_TSD_MASK  (1U << 2)
diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/misc_helper.c
index 0cef2f1a4c..53117f47de 100644
--- a/target/i386/tcg/sysemu/misc_helper.c
+++ b/target/i386/tcg/sysemu/misc_helper.c
@@ -84,6 +84,15 @@ void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
 {
     switch (reg) {
     case 0:
+        /*
+        * If we reach this point, the CR0 write intercept is disabled.
+        * But we could still exit if the hypervisor has requested the selective
+        * intercept for bits other than TS and MP
+        */
+        if ((env->intercept & INTERCEPT_SELECTIVE_CR0) &&
+            ((env->cr[0] ^ t0) & ~(CR0_TS_MASK | CR0_MP_MASK))) {
+            cpu_vmexit(env, SVM_EXIT_CR0_SEL_WRITE, 0, GETPC());
+        }
         cpu_x86_update_cr0(env, t0);
         break;
     case 3:
-- 
2.25.1


