From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PULL 22/33] tcg/tci: Implement add2, sub2
Date: Sat, 19 Jun 2021 11:14:41 -0700 [thread overview]
Message-ID: <20210619181452.877683-23-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org>
We already had the 32-bit versions for a 32-bit host; expand this
to 64-bit hosts as well. The 64-bit opcodes are new.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.h | 8 ++++----
tcg/tci.c | 40 ++++++++++++++++++++++++++--------------
tcg/tci/tcg-target.c.inc | 15 ++++++++-------
3 files changed, 38 insertions(+), 25 deletions(-)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 533f62bfcb..7b6089f304 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -122,11 +122,11 @@
#define TCG_TARGET_HAS_rot_i64 1
#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_muls2_i64 1
-#define TCG_TARGET_HAS_add2_i32 0
-#define TCG_TARGET_HAS_sub2_i32 0
+#define TCG_TARGET_HAS_add2_i32 1
+#define TCG_TARGET_HAS_sub2_i32 1
#define TCG_TARGET_HAS_mulu2_i32 1
-#define TCG_TARGET_HAS_add2_i64 0
-#define TCG_TARGET_HAS_sub2_i64 0
+#define TCG_TARGET_HAS_add2_i64 1
+#define TCG_TARGET_HAS_sub2_i64 1
#define TCG_TARGET_HAS_mulu2_i64 1
#define TCG_TARGET_HAS_muluh_i64 0
#define TCG_TARGET_HAS_mulsh_i64 0
diff --git a/tcg/tci.c b/tcg/tci.c
index ebe2eafa62..7103005889 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -193,7 +193,6 @@ static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1,
*c5 = extract32(insn, 28, 4);
}
-#if TCG_TARGET_REG_BITS == 32
static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1,
TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5)
{
@@ -204,7 +203,6 @@ static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1,
*r4 = extract32(insn, 24, 4);
*r5 = extract32(insn, 28, 4);
}
-#endif
static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition)
{
@@ -355,17 +353,14 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
for (;;) {
uint32_t insn;
TCGOpcode opc;
- TCGReg r0, r1, r2, r3, r4;
+ TCGReg r0, r1, r2, r3, r4, r5;
tcg_target_ulong t1;
TCGCond condition;
target_ulong taddr;
uint8_t pos, len;
uint32_t tmp32;
uint64_t tmp64;
-#if TCG_TARGET_REG_BITS == 32
- TCGReg r5;
uint64_t T1, T2;
-#endif
TCGMemOpIdx oi;
int32_t ofs;
void *ptr;
@@ -656,20 +651,22 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tb_ptr = ptr;
}
break;
-#if TCG_TARGET_REG_BITS == 32
+#if TCG_TARGET_REG_BITS == 32 || TCG_TARGET_HAS_add2_i32
case INDEX_op_add2_i32:
tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
T1 = tci_uint64(regs[r3], regs[r2]);
T2 = tci_uint64(regs[r5], regs[r4]);
tci_write_reg64(regs, r1, r0, T1 + T2);
break;
+#endif
+#if TCG_TARGET_REG_BITS == 32 || TCG_TARGET_HAS_sub2_i32
case INDEX_op_sub2_i32:
tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
T1 = tci_uint64(regs[r3], regs[r2]);
T2 = tci_uint64(regs[r5], regs[r4]);
tci_write_reg64(regs, r1, r0, T1 - T2);
break;
-#endif /* TCG_TARGET_REG_BITS == 32 */
+#endif
#if TCG_TARGET_HAS_mulu2_i32
case INDEX_op_mulu2_i32:
tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
@@ -799,6 +796,24 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
muls64(®s[r0], ®s[r1], regs[r2], regs[r3]);
break;
#endif
+#if TCG_TARGET_HAS_add2_i64
+ case INDEX_op_add2_i64:
+ tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
+ T1 = regs[r2] + regs[r4];
+ T2 = regs[r3] + regs[r5] + (T1 < regs[r2]);
+ regs[r0] = T1;
+ regs[r1] = T2;
+ break;
+#endif
+#if TCG_TARGET_HAS_add2_i64
+ case INDEX_op_sub2_i64:
+ tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
+ T1 = regs[r2] - regs[r4];
+ T2 = regs[r3] - regs[r5] - (regs[r2] < regs[r4]);
+ regs[r0] = T1;
+ regs[r1] = T2;
+ break;
+#endif
/* Shift/rotate operations (64 bit). */
@@ -1115,10 +1130,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
const char *op_name;
uint32_t insn;
TCGOpcode op;
- TCGReg r0, r1, r2, r3, r4;
-#if TCG_TARGET_REG_BITS == 32
- TCGReg r5;
-#endif
+ TCGReg r0, r1, r2, r3, r4, r5;
tcg_target_ulong i1;
int32_t s2;
TCGCond c;
@@ -1316,15 +1328,15 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
str_r(r2), str_r(r3));
break;
-#if TCG_TARGET_REG_BITS == 32
case INDEX_op_add2_i32:
+ case INDEX_op_add2_i64:
case INDEX_op_sub2_i32:
+ case INDEX_op_sub2_i64:
tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %s",
op_name, str_r(r0), str_r(r1), str_r(r2),
str_r(r3), str_r(r4), str_r(r5));
break;
-#endif
case INDEX_op_qemu_ld_i64:
case INDEX_op_qemu_st_i64:
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index e48dbc95d2..9651e7a8f1 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -134,11 +134,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_brcond_i64:
return C_O0_I2(r, r);
-#if TCG_TARGET_REG_BITS == 32
- /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
case INDEX_op_add2_i32:
+ case INDEX_op_add2_i64:
case INDEX_op_sub2_i32:
+ case INDEX_op_sub2_i64:
return C_O2_I4(r, r, r, r, r, r);
+
+#if TCG_TARGET_REG_BITS == 32
case INDEX_op_brcond2_i32:
return C_O0_I4(r, r, r, r);
#endif
@@ -467,7 +469,6 @@ static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op,
tcg_out32(s, insn);
}
-#if TCG_TARGET_REG_BITS == 32
static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2,
TCGReg r3, TCGReg r4, TCGReg r5)
@@ -483,7 +484,6 @@ static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op,
insn = deposit32(insn, 28, 4, r5);
tcg_out32(s, insn);
}
-#endif
static void tcg_out_ldst(TCGContext *s, TCGOpcode op, TCGReg val,
TCGReg base, intptr_t offset)
@@ -717,12 +717,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_op_rr(s, opc, args[0], args[1]);
break;
-#if TCG_TARGET_REG_BITS == 32
- case INDEX_op_add2_i32:
- case INDEX_op_sub2_i32:
+ CASE_32_64(add2)
+ CASE_32_64(sub2)
tcg_out_op_rrrrrr(s, opc, args[0], args[1], args[2],
args[3], args[4], args[5]);
break;
+
+#if TCG_TARGET_REG_BITS == 32
case INDEX_op_brcond2_i32:
tcg_out_op_rrrrrc(s, INDEX_op_setcond2_i32, TCG_REG_TMP,
args[0], args[1], args[2], args[3], args[4]);
--
2.25.1
next prev parent reply other threads:[~2021-06-19 18:30 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-19 18:14 [PULL 00/33] tcg patch queue Richard Henderson
2021-06-19 18:14 ` [PULL 01/33] tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode Richard Henderson
2021-06-19 18:14 ` [PULL 02/33] tcg: Add tcg_call_flags Richard Henderson
2021-06-19 18:14 ` [PULL 03/33] accel/tcg/plugin-gen: Drop inline markers Richard Henderson
2021-06-19 18:14 ` [PULL 04/33] plugins: Drop tcg_flags from struct qemu_plugin_dyn_cb Richard Henderson
2021-06-19 18:14 ` [PULL 05/33] accel/tcg: Add tcg call flags to plugins helpers Richard Henderson
2021-06-19 18:14 ` [PULL 06/33] tcg: Store the TCGHelperInfo in the TCGOp for call Richard Henderson
2021-06-19 18:14 ` [PULL 07/33] tcg: Add tcg_call_func Richard Henderson
2021-06-19 18:14 ` [PULL 08/33] tcg: Build ffi data structures for helpers Richard Henderson
2021-06-19 18:14 ` [PULL 09/33] tcg/tci: Improve tcg_target_call_clobber_regs Richard Henderson
2021-06-19 18:14 ` [PULL 10/33] tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order Richard Henderson
2021-06-19 18:14 ` [PULL 11/33] tcg/tci: Use ffi for calls Richard Henderson
2021-06-19 18:14 ` [PULL 12/33] tcg/tci: Reserve r13 for a temporary Richard Henderson
2021-06-19 18:14 ` [PULL 13/33] tcg/tci: Emit setcond before brcond Richard Henderson
2021-06-19 18:14 ` [PULL 14/33] tcg/tci: Remove tci_write_reg Richard Henderson
2021-06-19 18:14 ` [PULL 15/33] tcg/tci: Change encoding to uint32_t units Richard Henderson
2021-06-19 18:14 ` [PULL 16/33] tcg/tci: Implement goto_ptr Richard Henderson
2021-06-19 18:14 ` [PULL 17/33] tcg/tci: Implement movcond Richard Henderson
2021-06-19 18:14 ` [PULL 18/33] tcg/tci: Implement andc, orc, eqv, nand, nor Richard Henderson
2021-06-19 18:14 ` [PULL 19/33] tcg/tci: Implement extract, sextract Richard Henderson
2021-06-19 18:14 ` [PULL 20/33] tcg/tci: Implement clz, ctz, ctpop Richard Henderson
2021-06-19 18:14 ` [PULL 21/33] tcg/tci: Implement mulu2, muls2 Richard Henderson
2021-06-19 18:14 ` Richard Henderson [this message]
2021-06-19 18:14 ` [PULL 23/33] tcg/tci: Split out tci_qemu_ld, tci_qemu_st Richard Henderson
2021-06-19 18:14 ` [PULL 24/33] Revert "tcg/tci: Use exec/cpu_ldst.h interfaces" Richard Henderson
2021-06-19 18:14 ` [PULL 25/33] tcg/tci: Remove the qemu_ld/st_type macros Richard Henderson
2021-06-19 18:14 ` [PULL 26/33] tcg/tci: Use {set,clear}_helper_retaddr Richard Henderson
2021-06-19 18:14 ` [PULL 27/33] tests/tcg: Increase timeout for TCI Richard Henderson
2021-06-19 18:14 ` [PULL 28/33] accel/tcg: Probe the proper permissions for atomic ops Richard Henderson
2021-06-19 18:14 ` [PULL 29/33] tcg/sparc: Fix temp_allocate_frame vs sparc stack bias Richard Henderson
2021-06-19 18:14 ` [PULL 30/33] tcg: Allocate sufficient storage in temp_allocate_frame Richard Henderson
2021-09-01 10:52 ` Richard W.M. Jones
2021-09-01 12:55 ` Daniel P. Berrangé
2021-06-19 18:14 ` [PULL 31/33] tcg: Restart when exhausting the stack frame Richard Henderson
2021-06-19 18:14 ` [PULL 32/33] tcg: expose TCGCond manipulation routines Richard Henderson
2021-06-19 18:14 ` [PULL 33/33] util/oslib-win32: Fix fatal assertion in qemu_try_memalign Richard Henderson
2021-06-19 21:50 ` [PULL 00/33] tcg patch queue Richard Henderson
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