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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Aurelien Jarno" <aurelien@aurel32.net>,
	"Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PULL 13/15] target/mips: Optimize regnames[] arrays
Date: Fri, 25 Jun 2021 11:23:27 +0200	[thread overview]
Message-ID: <20210625092329.1529100-14-f4bug@amsat.org> (raw)
In-Reply-To: <20210625092329.1529100-1-f4bug@amsat.org>

Since all entries are no more than 3/4/6 bytes (including nul
terminator), can save space and pie runtime relocations by
declaring regnames[] as array of 3/4/6 const char.

Inspired-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210617174323.2900831-10-f4bug@amsat.org>
---
 target/mips/internal.h          | 2 +-
 target/mips/cpu.c               | 2 +-
 target/mips/tcg/msa_translate.c | 2 +-
 target/mips/tcg/mxu_translate.c | 4 ++--
 target/mips/tcg/translate.c     | 4 ++--
 5 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 18d5da64a57..eecdd101169 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -74,7 +74,7 @@ struct mips_def_t {
     int32_t SAARP;
 };
 
-extern const char regnames[32][4];
+extern const char regnames[32][3];
 extern const char fregnames[32][4];
 
 extern const struct mips_def_t mips_defs[];
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 96236abc006..d426918291a 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -35,7 +35,7 @@
 #include "qapi/qapi-commands-machine-target.h"
 #include "fpu_helper.h"
 
-const char regnames[32][4] = {
+const char regnames[32][3] = {
     "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
     "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
     "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index ae6587edf69..b0df4f85dfe 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -255,7 +255,7 @@ enum {
     OPC_BINSRI_df   = (0x7 << 23) | OPC_MSA_BIT_09,
 };
 
-static const char * const msaregnames[] = {
+static const char msaregnames[][6] = {
     "w0.d0",  "w0.d1",  "w1.d0",  "w1.d1",
     "w2.d0",  "w2.d1",  "w3.d0",  "w3.d1",
     "w4.d0",  "w4.d1",  "w5.d0",  "w5.d1",
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index fb0a811af6c..963d4ba8b13 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -447,9 +447,9 @@ enum {
 static TCGv mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
 static TCGv mxu_CR;
 
-static const char * const mxuregnames[] = {
+static const char mxuregnames[][4] = {
     "XR1",  "XR2",  "XR3",  "XR4",  "XR5",  "XR6",  "XR7",  "XR8",
-    "XR9",  "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "MXU_CR",
+    "XR9",  "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "XCR",
 };
 
 void mxu_translate_init(void)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index d248b5e5d21..b4a454ec09b 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -1280,11 +1280,11 @@ TCGv_i64 fpu_f64[32];
 #define DISAS_STOP       DISAS_TARGET_0
 #define DISAS_EXIT       DISAS_TARGET_1
 
-static const char * const regnames_HI[] = {
+static const char regnames_HI[][4] = {
     "HI0", "HI1", "HI2", "HI3",
 };
 
-static const char * const regnames_LO[] = {
+static const char regnames_LO[][4] = {
     "LO0", "LO1", "LO2", "LO3",
 };
 
-- 
2.31.1



  parent reply	other threads:[~2021-06-25  9:54 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-25  9:23 [PULL 00/15] MIPS patches for 2021-06-25 Philippe Mathieu-Daudé
2021-06-25  9:23 ` [PULL 01/15] target/mips: Fix potential integer overflow (CID 1452921) Philippe Mathieu-Daudé
2021-06-25  9:23 ` [PULL 02/15] target/mips: Fix TCG temporary leaks in gen_pool32a5_nanomips_insn() Philippe Mathieu-Daudé
2021-06-25  9:23 ` [PULL 03/15] target/mips: Fix more TCG temporary leaks in gen_pool32a5_nanomips_insn Philippe Mathieu-Daudé
2021-06-25  9:23 ` [PULL 04/15] target/mips: Raise exception when DINSV opcode used with DSP disabled Philippe Mathieu-Daudé
2021-06-25  9:23 ` [PULL 05/15] target/mips: Do not abort on invalid instruction Philippe Mathieu-Daudé
2021-06-25  9:23 ` [PULL 06/15] target/mips: Move TCG trace events to tcg/ sub directory Philippe Mathieu-Daudé
2021-06-25  9:23 ` [PULL 07/15] target/mips: Move translate.h " Philippe Mathieu-Daudé
2021-06-25  9:23 ` [PULL 08/15] target/mips: Restrict some system specific declarations to sysemu Philippe Mathieu-Daudé
2021-06-25  9:23 ` [PULL 09/15] target/mips: Remove SmartMIPS / MDMX unuseful comments Philippe Mathieu-Daudé
2021-06-25  9:23 ` [PULL 10/15] target/mips: Remove microMIPS BPOSGE32 / BPOSGE64 unuseful cases Philippe Mathieu-Daudé
2021-06-25  9:23 ` [PULL 11/15] target/mips: fix emulation of nanoMIPS BPOSGE32 instruction Philippe Mathieu-Daudé
2021-06-25  9:23 ` [PULL 12/15] target/mips: Constify host_to_mips_errno[] Philippe Mathieu-Daudé
2021-06-25  9:23 ` Philippe Mathieu-Daudé [this message]
2021-06-25  9:23 ` [PULL 14/15] target/mips: Remove pointless gen_msa() Philippe Mathieu-Daudé
2021-06-25  9:23 ` [PULL 15/15] target/mips: Merge msa32/msa64 decodetree definitions Philippe Mathieu-Daudé
2021-06-28 13:00 ` [PULL 00/15] MIPS patches for 2021-06-25 Peter Maydell

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