From: Alessandro Di Federico via <qemu-devel@nongnu.org>
To: qemu-devel@nongnu.org
Cc: tsimpson@quicinc.com, bcain@quicinc.com, babush@rev.ng,
nizzo@rev.ng, richard.henderson@linaro.org,
Alessandro Di Federico <ale@rev.ng>
Subject: [PATCH v6 05/12] target/hexagon: introduce new helper functions
Date: Tue, 20 Jul 2021 14:30:24 +0200 [thread overview]
Message-ID: <20210720123031.1101682-6-ale.qemu@rev.ng> (raw)
In-Reply-To: <20210720123031.1101682-1-ale.qemu@rev.ng>
From: Niccolò Izzo <nizzo@rev.ng>
These helpers will be employed by the idef-parser generated code.
Signed-off-by: Alessandro Di Federico <ale@rev.ng>
Signed-off-by: Niccolò Izzo <nizzo@rev.ng>
---
target/hexagon/genptr.h | 15 +++++-
target/hexagon/macros.h | 9 ++++
target/hexagon/genptr.c | 113 +++++++++++++++++++++++++++++++++++++---
3 files changed, 129 insertions(+), 8 deletions(-)
diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h
index d71dd7e1ce..6bd54cc7f4 100644
--- a/target/hexagon/genptr.h
+++ b/target/hexagon/genptr.h
@@ -24,7 +24,8 @@
extern const SemanticInsn opcode_genptr[];
-void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot);
+void gen_store32(DisasContext *ctx, TCGv vaddr, TCGv src, tcg_target_long width,
+ uint32_t slot);
void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx,
uint32_t slot);
void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx,
@@ -44,6 +45,17 @@ void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, DisasContext *ctx,
TCGv gen_read_preg(TCGv pred, uint8_t num);
void gen_log_reg_write(int rnum, TCGv val);
void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val);
+void gen_write_new_pc(TCGv addr);
+void gen_set_usr_field(int field, TCGv val);
+void gen_set_usr_fieldi(int field, int x);
+void gen_sat_i32(TCGv dest, TCGv source, int width);
+void gen_sat_i32_ovfl(TCGv ovfl, TCGv dest, TCGv source, int width);
+void gen_satu_i32(TCGv dest, TCGv source, int width);
+void gen_satu_i32_ovfl(TCGv ovfl, TCGv dest, TCGv source, int width);
+void gen_sat_i64(TCGv_i64 dest, TCGv_i64 source, int width);
+void gen_sat_i64_ovfl(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width);
+void gen_satu_i64(TCGv_i64 dest, TCGv_i64 source, int width);
+void gen_satu_i64_ovfl(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width);
TCGv gen_8bitsof(TCGv result, TCGv value);
void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src);
TCGv gen_get_byte(TCGv result, int N, TCGv src, bool sign);
@@ -51,5 +63,6 @@ TCGv gen_get_byte_i64(TCGv result, int N, TCGv_i64 src, bool sign);
TCGv gen_get_half(TCGv result, int N, TCGv src, bool sign);
void gen_set_half(int N, TCGv result, TCGv src);
void gen_set_half_i64(int N, TCGv_i64 result, TCGv src);
+TCGv gen_read_reg(TCGv result, int num);
#endif
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index cd4f878fcf..2dabdbb49e 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -180,7 +180,16 @@
#define MEM_STORE8(VA, DATA, SLOT) log_store64(env, VA, DATA, 8, SLOT)
#endif
+#ifdef QEMU_GENERATE
+static inline void gen_cancel(uint32_t slot)
+{
+ tcg_gen_ori_tl(hex_slot_cancelled, hex_slot_cancelled, 1 << slot);
+}
+
+#define CANCEL gen_cancel(slot);
+#else
#define CANCEL cancel_slot(env, slot)
+#endif
#define LOAD_CANCEL(EA) do { CANCEL; } while (0)
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 5e7f446657..b7eca94de7 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -28,6 +28,12 @@
#include "gen_tcg.h"
#include "genptr.h"
+TCGv gen_read_reg(TCGv result, int num)
+{
+ tcg_gen_mov_tl(result, hex_gpr[num]);
+ return result;
+}
+
TCGv gen_read_preg(TCGv pred, uint8_t num)
{
tcg_gen_mov_tl(pred, hex_pred[num]);
@@ -388,18 +394,19 @@ static inline void gen_store_conditional8(DisasContext *ctx,
tcg_gen_movi_tl(hex_llsc_addr, ~0);
}
-void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot)
+void gen_store32(DisasContext *ctx, TCGv vaddr, TCGv src, tcg_target_long width,
+ uint32_t slot)
{
tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
tcg_gen_movi_tl(hex_store_width[slot], width);
tcg_gen_mov_tl(hex_store_val32[slot], src);
+ ctx->store_width[slot] = width;
}
void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx,
uint32_t slot)
{
- gen_store32(vaddr, src, 1, slot);
- ctx->store_width[slot] = 1;
+ gen_store32(ctx, vaddr, src, 1, slot);
}
void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, DisasContext *ctx,
@@ -413,8 +420,7 @@ void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, DisasContext *ctx,
void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx,
uint32_t slot)
{
- gen_store32(vaddr, src, 2, slot);
- ctx->store_width[slot] = 2;
+ gen_store32(ctx, vaddr, src, 2, slot);
}
void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, DisasContext *ctx,
@@ -428,8 +434,7 @@ void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, DisasContext *ctx,
void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx,
uint32_t slot)
{
- gen_store32(vaddr, src, 4, slot);
- ctx->store_width[slot] = 4;
+ gen_store32(ctx, vaddr, src, 4, slot);
}
void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, DisasContext *ctx,
@@ -468,5 +473,99 @@ TCGv gen_8bitsof(TCGv result, TCGv value)
return result;
}
+void gen_set_usr_field(int field, TCGv val)
+{
+ tcg_gen_deposit_tl(hex_gpr[HEX_REG_USR], hex_gpr[HEX_REG_USR], val,
+ reg_field_info[field].offset,
+ reg_field_info[field].width);
+}
+
+void gen_set_usr_fieldi(int field, int x)
+{
+ TCGv val = tcg_const_tl(x);
+ gen_set_usr_field(field, val);
+ tcg_temp_free(val);
+}
+
+void gen_write_new_pc(TCGv addr)
+{
+ /* If there are multiple branches in a packet, ignore the second one */
+ TCGv zero = tcg_const_tl(0);
+ tcg_gen_movcond_tl(TCG_COND_NE, hex_next_PC, hex_branch_taken, zero,
+ hex_next_PC, addr);
+ tcg_gen_movi_tl(hex_branch_taken, 1);
+ tcg_temp_free(zero);
+}
+
+void gen_sat_i32(TCGv dest, TCGv source, int width)
+{
+ TCGv max_val = tcg_const_tl((1 << (width - 1)) - 1);
+ TCGv min_val = tcg_const_tl(-(1 << (width - 1)));
+ tcg_gen_smin_tl(dest, source, max_val);
+ tcg_gen_smax_tl(dest, dest, min_val);
+ tcg_temp_free(max_val);
+ tcg_temp_free(min_val);
+}
+
+void gen_sat_i32_ovfl(TCGv ovfl, TCGv dest, TCGv source, int width)
+{
+ gen_sat_i32(dest, source, width);
+ tcg_gen_setcond_tl(TCG_COND_NE, ovfl, source, dest);
+}
+
+void gen_satu_i32(TCGv dest, TCGv source, int width)
+{
+ TCGv max_val = tcg_const_tl((1 << width) - 1);
+ tcg_gen_movcond_tl(TCG_COND_GTU, dest, source, max_val, max_val, source);
+ TCGv zero = tcg_const_tl(0);
+ tcg_gen_movcond_tl(TCG_COND_LT, dest, source, zero, zero, dest);
+ tcg_temp_free(max_val);
+ tcg_temp_free(zero);
+}
+
+void gen_satu_i32_ovfl(TCGv ovfl, TCGv dest, TCGv source, int width)
+{
+ gen_satu_i32(dest, source, width);
+ tcg_gen_setcond_tl(TCG_COND_NE, ovfl, source, dest);
+}
+
+void gen_sat_i64(TCGv_i64 dest, TCGv_i64 source, int width)
+{
+ TCGv_i64 max_val = tcg_const_i64((1 << (width - 1)) - 1);
+ TCGv_i64 min_val = tcg_const_i64(-(1 << (width - 1)));
+ tcg_gen_smin_i64(dest, source, max_val);
+ tcg_gen_smax_i64(dest, dest, min_val);
+ tcg_temp_free_i64(max_val);
+ tcg_temp_free_i64(min_val);
+}
+
+void gen_sat_i64_ovfl(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width)
+{
+ gen_sat_i64(dest, source, width);
+ TCGv_i64 ovfl_64 = tcg_temp_new_i64();
+ tcg_gen_setcond_i64(TCG_COND_NE, ovfl_64, dest, source);
+ tcg_gen_trunc_i64_tl(ovfl, ovfl_64);
+ tcg_temp_free_i64(ovfl_64);
+}
+
+void gen_satu_i64(TCGv_i64 dest, TCGv_i64 source, int width)
+{
+ TCGv_i64 max_val = tcg_const_i64((1 << width) - 1);
+ tcg_gen_movcond_i64(TCG_COND_GTU, dest, source, max_val, max_val, source);
+ TCGv_i64 zero = tcg_const_i64(0);
+ tcg_gen_movcond_i64(TCG_COND_LT, dest, source, zero, zero, dest);
+ tcg_temp_free_i64(max_val);
+ tcg_temp_free_i64(zero);
+}
+
+void gen_satu_i64_ovfl(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width)
+{
+ gen_sat_i64(dest, source, width);
+ TCGv_i64 ovfl_64 = tcg_temp_new_i64();
+ tcg_gen_setcond_i64(TCG_COND_NE, ovfl_64, dest, source);
+ tcg_gen_trunc_i64_tl(ovfl, ovfl_64);
+ tcg_temp_free_i64(ovfl_64);
+}
+
#include "tcg_funcs_generated.c.inc"
#include "tcg_func_table_generated.c.inc"
--
2.32.0
next prev parent reply other threads:[~2021-07-20 12:33 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-20 12:30 [PATCH v6 00/12] target/hexagon: introduce idef-parser Alessandro Di Federico via
2021-07-20 12:30 ` [PATCH v6 01/12] target/hexagon: update MAINTAINERS for idef-parser Alessandro Di Federico via
2021-09-07 18:09 ` Taylor Simpson
2021-07-20 12:30 ` [PATCH v6 02/12] target/hexagon: import README " Alessandro Di Federico via
2021-09-07 18:09 ` Taylor Simpson
2021-07-20 12:30 ` [PATCH v6 03/12] target/hexagon: make slot number an unsigned Alessandro Di Federico via
2021-09-07 18:09 ` Taylor Simpson
2021-07-20 12:30 ` [PATCH v6 04/12] target/hexagon: make helper functions non-static Alessandro Di Federico via
2021-07-20 12:30 ` Alessandro Di Federico via [this message]
2021-09-07 18:09 ` [PATCH v6 05/12] target/hexagon: introduce new helper functions Taylor Simpson
2021-07-20 12:30 ` [PATCH v6 06/12] target/hexagon: expose next PC in DisasContext Alessandro Di Federico via
2021-07-20 12:30 ` [PATCH v6 07/12] target/hexagon: prepare input for the idef-parser Alessandro Di Federico via
2021-09-07 18:09 ` Taylor Simpson
2021-10-18 11:23 ` Anton Johansson via
2021-10-28 15:44 ` Taylor Simpson
2021-07-20 12:30 ` [PATCH v6 08/12] target/hexagon: import lexer for idef-parser Alessandro Di Federico via
2021-09-07 18:08 ` Taylor Simpson
2021-10-18 11:37 ` Anton Johansson via
2021-10-28 15:49 ` Taylor Simpson
2021-07-20 12:30 ` [PATCH v6 09/12] target/hexagon: import parser " Alessandro Di Federico via
2021-09-07 18:08 ` Taylor Simpson
2021-09-08 6:35 ` Richard Henderson
2021-10-18 11:42 ` Anton Johansson via
2021-10-28 15:56 ` Taylor Simpson
2021-07-20 12:30 ` [PATCH v6 10/12] target/hexagon: call idef-parser functions Alessandro Di Federico via
2021-07-20 12:30 ` [PATCH v6 11/12] target/hexagon: import additional tests Alessandro Di Federico via
2021-07-20 12:30 ` [PATCH v6 12/12] gitlab-ci: do not use qemu-project Docker registry Alessandro Di Federico via
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