From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH for-6.2 18/23] target/riscv: Remove exit_tb and lookup_and_goto_ptr
Date: Tue, 20 Jul 2021 20:41:50 -1000 [thread overview]
Message-ID: <20210721064155.645508-19-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210721064155.645508-1-richard.henderson@linaro.org>
GDB single-stepping is now handled generically, which means
we don't need to do anything in the wrappers.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/translate.c | 29 +------------------
.../riscv/insn_trans/trans_privileged.c.inc | 4 +--
target/riscv/insn_trans/trans_rvi.c.inc | 6 ++--
target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
4 files changed, 7 insertions(+), 34 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 6983be5723..b4cc79a494 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -131,33 +131,6 @@ static void generate_exception_mtval(DisasContext *ctx, int excp)
ctx->base.is_jmp = DISAS_NORETURN;
}
-static void gen_exception_debug(void)
-{
- TCGv_i32 helper_tmp = tcg_const_i32(EXCP_DEBUG);
- gen_helper_raise_exception(cpu_env, helper_tmp);
- tcg_temp_free_i32(helper_tmp);
-}
-
-/* Wrapper around tcg_gen_exit_tb that handles single stepping */
-static void exit_tb(DisasContext *ctx)
-{
- if (ctx->base.singlestep_enabled) {
- gen_exception_debug();
- } else {
- tcg_gen_exit_tb(NULL, 0);
- }
-}
-
-/* Wrapper around tcg_gen_lookup_and_goto_ptr that handles single stepping */
-static void lookup_and_goto_ptr(DisasContext *ctx)
-{
- if (ctx->base.singlestep_enabled) {
- gen_exception_debug();
- } else {
- tcg_gen_lookup_and_goto_ptr();
- }
-}
-
static void gen_exception_illegal(DisasContext *ctx)
{
generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
@@ -176,7 +149,7 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
tcg_gen_exit_tb(ctx->base.tb, n);
} else {
tcg_gen_movi_tl(cpu_pc, dest);
- lookup_and_goto_ptr(ctx);
+ tcg_gen_lookup_and_goto_ptr();
}
}
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index a7afcb15ce..75c6ef80a6 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -78,7 +78,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
if (has_ext(ctx, RVS)) {
gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
- exit_tb(ctx); /* no chaining */
+ tcg_gen_exit_tb(NULL, 0); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
} else {
return false;
@@ -94,7 +94,7 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)
#ifndef CONFIG_USER_ONLY
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
- exit_tb(ctx); /* no chaining */
+ tcg_gen_exit_tb(NULL, 0); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
return true;
#else
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 6e736c9d0d..aef3e84ca8 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -72,7 +72,7 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
if (a->rd != 0) {
tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
}
- lookup_and_goto_ptr(ctx);
+ tcg_gen_lookup_and_goto_ptr();
if (misaligned) {
gen_set_label(misaligned);
@@ -461,7 +461,7 @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
* however we need to end the translation block
*/
tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
- exit_tb(ctx);
+ tcg_gen_exit_tb(NULL, 0);
ctx->base.is_jmp = DISAS_NORETURN;
return true;
}
@@ -481,7 +481,7 @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
#define RISCV_OP_CSR_POST do {\
gen_set_gpr(a->rd, dest); \
tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); \
- exit_tb(ctx); \
+ tcg_gen_exit_tb(NULL, 0); \
ctx->base.is_jmp = DISAS_NORETURN; \
tcg_temp_free(source1); \
tcg_temp_free(csr_store); \
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 83d9a285ba..56eb775cef 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -42,7 +42,7 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
gen_helper_vsetvl(dst, cpu_env, s1, s2);
gen_set_gpr(a->rd, dst);
tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
- lookup_and_goto_ptr(ctx);
+ tcg_gen_lookup_and_goto_ptr();
ctx->base.is_jmp = DISAS_NORETURN;
tcg_temp_free(s1);
--
2.25.1
next prev parent reply other threads:[~2021-07-21 6:53 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-21 6:41 [PATCH for-6.2 00/23] tcg: gdb singlestep reorg Richard Henderson
2021-07-21 6:41 ` [PATCH for-6.2 01/23] accel/tcg: Handle gdb singlestep in cpu_tb_exec Richard Henderson
2021-07-21 6:41 ` [PATCH for-6.2 02/23] target/alpha: Drop checks for singlestep_enabled Richard Henderson
2021-07-21 6:41 ` [PATCH for-6.2 03/23] target/avr: " Richard Henderson
2021-07-21 18:00 ` Philippe Mathieu-Daudé
2021-07-22 11:18 ` Michael Rolnik
2021-07-21 6:41 ` [PATCH for-6.2 04/23] target/cris: " Richard Henderson
2021-07-21 6:41 ` [PATCH for-6.2 05/23] target/hexagon: " Richard Henderson
2021-07-21 6:41 ` [PATCH for-6.2 06/23] target/arm: " Richard Henderson
2021-07-21 6:41 ` [PATCH for-6.2 07/23] target/hppa: " Richard Henderson
2021-07-21 17:50 ` Philippe Mathieu-Daudé
2021-07-21 6:41 ` [PATCH for-6.2 08/23] target/i386: Check CF_NO_GOTO_TB for dc->jmp_opt Richard Henderson
2021-07-21 6:41 ` [PATCH for-6.2 09/23] target/i386: Drop check for singlestep_enabled Richard Henderson
2021-07-21 6:41 ` [PATCH for-6.2 10/23] target/m68k: Drop checks " Richard Henderson
2021-07-21 8:54 ` Laurent Vivier
2021-07-21 6:41 ` [PATCH for-6.2 11/23] target/microblaze: Check CF_NO_GOTO_TB for DISAS_JUMP Richard Henderson
2021-07-21 6:41 ` [PATCH for-6.2 12/23] target/microblaze: Drop checks for singlestep_enabled Richard Henderson
2021-07-21 6:41 ` [PATCH for-6.2 13/23] target/mips: Fix single stepping Richard Henderson
2021-07-21 6:41 ` [PATCH for-6.2 14/23] target/mips: Drop exit checks for singlestep_enabled Richard Henderson
2021-07-21 17:51 ` Philippe Mathieu-Daudé
2021-07-21 6:41 ` [PATCH for-6.2 15/23] target/openrisc: Drop " Richard Henderson
2021-07-21 6:41 ` [PATCH for-6.2 16/23] target/ppc: Drop exit " Richard Henderson
2021-07-21 6:41 ` [PATCH for-6.2 17/23] target/riscv: Remove dead code after exception Richard Henderson
2021-07-21 6:41 ` Richard Henderson [this message]
2021-07-21 6:41 ` [PATCH for-6.2 19/23] target/rx: Drop checks for singlestep_enabled Richard Henderson
2021-07-21 6:41 ` [PATCH for-6.2 20/23] target/s390x: Drop check " Richard Henderson
2021-07-21 6:41 ` [PATCH for-6.2 21/23] target/sh4: " Richard Henderson
2021-07-21 17:51 ` Philippe Mathieu-Daudé
2021-07-21 6:41 ` [PATCH for-6.2 22/23] target/tricore: " Richard Henderson
2021-07-21 6:41 ` [PATCH for-6.2 23/23] target/xtensa: " Richard Henderson
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