From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>
Subject: [Intel-gfx] [PATCH v3 25/30] drm/i915/dg2: Add vswing programming for SNPS phys
Date: Fri, 23 Jul 2021 10:42:34 -0700 [thread overview]
Message-ID: <20210723174239.1551352-26-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20210723174239.1551352-1-matthew.d.roper@intel.com>
Vswing programming for SNPS PHYs is just a single step -- look up the
value that corresponds to the voltage level from a table and program it
into the SNPS_PHY_TX_EQ register.
Bspec: 53920
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 23 ++++++--
drivers/gpu/drm/i915/display/intel_snps_phy.c | 54 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_snps_phy.h | 4 ++
drivers/gpu/drm/i915/i915_reg.h | 5 ++
4 files changed, 83 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 929a95ddb316..ade03cf41caa 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1496,6 +1496,16 @@ static int intel_ddi_dp_level(struct intel_dp *intel_dp)
return translate_signal_level(intel_dp, signal_levels);
}
+static void
+dg2_set_signal_levels(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+ int level = intel_ddi_dp_level(intel_dp);
+
+ intel_snps_phy_ddi_vswing_sequence(encoder, level);
+}
+
static void
tgl_set_signal_levels(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
@@ -2563,7 +2573,10 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
*/
/* 7.e Configure voltage swing and related IO settings */
- tgl_ddi_vswing_sequence(encoder, crtc_state, level);
+ if (IS_DG2(dev_priv))
+ intel_snps_phy_ddi_vswing_sequence(encoder, level);
+ else
+ tgl_ddi_vswing_sequence(encoder, crtc_state, level);
/*
* 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
@@ -3102,7 +3115,9 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
"[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
connector->base.id, connector->name);
- if (DISPLAY_VER(dev_priv) >= 12)
+ if (IS_DG2(dev_priv))
+ intel_snps_phy_ddi_vswing_sequence(encoder, U32_MAX);
+ else if (DISPLAY_VER(dev_priv) >= 12)
tgl_ddi_vswing_sequence(encoder, crtc_state, level);
else if (DISPLAY_VER(dev_priv) == 11)
icl_ddi_vswing_sequence(encoder, crtc_state, level);
@@ -4075,7 +4090,9 @@ intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
dig_port->dp.set_link_train = intel_ddi_set_link_train;
dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train;
- if (DISPLAY_VER(dev_priv) >= 12)
+ if (IS_DG2(dev_priv))
+ dig_port->dp.set_signal_levels = dg2_set_signal_levels;
+ else if (DISPLAY_VER(dev_priv) >= 12)
dig_port->dp.set_signal_levels = tgl_set_signal_levels;
else if (DISPLAY_VER(dev_priv) >= 11)
dig_port->dp.set_signal_levels = icl_set_signal_levels;
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index 1317b4e94b50..77759bda98a4 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -21,6 +21,60 @@
* since it is not handled by the shared DPLL framework as on other platforms.
*/
+static const u32 dg2_ddi_translations[] = {
+ /* VS 0, pre-emph 0 */
+ REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 26),
+
+ /* VS 0, pre-emph 1 */
+ REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 33) |
+ REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 6),
+
+ /* VS 0, pre-emph 2 */
+ REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 38) |
+ REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 12),
+
+ /* VS 0, pre-emph 3 */
+ REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 43) |
+ REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 19),
+
+ /* VS 1, pre-emph 0 */
+ REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 39),
+
+ /* VS 1, pre-emph 1 */
+ REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 44) |
+ REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 8),
+
+ /* VS 1, pre-emph 2 */
+ REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 47) |
+ REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 15),
+
+ /* VS 2, pre-emph 0 */
+ REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 52),
+
+ /* VS 2, pre-emph 1 */
+ REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 51) |
+ REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 10),
+
+ /* VS 3, pre-emph 0 */
+ REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 62),
+};
+
+void intel_snps_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
+ u32 level)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+ int n_entries, ln;
+
+ n_entries = ARRAY_SIZE(dg2_ddi_translations);
+ if (level >= n_entries)
+ level = n_entries - 1;
+
+ for (ln = 0; ln < 4; ln++)
+ intel_de_write(dev_priv, SNPS_PHY_TX_EQ(ln, phy),
+ dg2_ddi_translations[level]);
+}
+
/*
* Basic DP link rates with 100 MHz reference clock.
*/
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.h b/drivers/gpu/drm/i915/display/intel_snps_phy.h
index ca4c2a25182b..3ce92d424f66 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.h
@@ -6,6 +6,8 @@
#ifndef __INTEL_SNPS_PHY_H__
#define __INTEL_SNPS_PHY_H__
+#include <linux/types.h>
+
struct intel_encoder;
struct intel_crtc_state;
struct intel_mpllb_state;
@@ -21,5 +23,7 @@ int intel_mpllb_calc_port_clock(struct intel_encoder *encoder,
const struct intel_mpllb_state *pll_state);
int intel_snps_phy_check_hdmi_link_rate(int clock);
+void intel_snps_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
+ u32 level);
#endif /* __INTEL_SNPS_PHY_H__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dc0002c1efda..2e028350c32d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2340,6 +2340,11 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define SNPS_PHY_REF_CONTROL(phy) _MMIO_SNPS(phy, 0x168188)
#define SNPS_PHY_REF_CONTROL_REF_RANGE REG_GENMASK(31, 27)
+#define SNPS_PHY_TX_EQ(ln, phy) _MMIO_SNPS_LN(ln, phy, 0x168300)
+#define SNPS_PHY_TX_EQ_MAIN REG_GENMASK(23, 18)
+#define SNPS_PHY_TX_EQ_POST REG_GENMASK(15, 10)
+#define SNPS_PHY_TX_EQ_PRE REG_GENMASK(7, 2)
+
/* The spec defines this only for BXT PHY0, but lets assume that this
* would exist for PHY1 too if it had a second channel.
*/
--
2.25.4
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next prev parent reply other threads:[~2021-07-23 17:43 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-23 17:42 [Intel-gfx] [PATCH v3 00/30] Begin enabling Xe_HP SDV and DG2 platforms Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 01/30] drm/i915/xehpsdv: Correct parameters for IS_XEHPSDV_GT_STEP() Matt Roper
2021-07-27 18:34 ` Yokoyama, Caz
2021-07-27 18:38 ` Matt Roper
2021-07-27 19:00 ` Yokoyama, Caz
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 02/30] drm/i915/xehp: Extra media engines - Part 1 (engine definitions) Matt Roper
2021-07-23 17:54 ` Lucas De Marchi
2021-07-23 17:55 ` Matt Roper
2021-07-23 19:10 ` [Intel-gfx] [PATCH v4 2/2] " Matt Roper
2021-07-24 0:47 ` Lucas De Marchi
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 03/30] drm/i915/xehp: Extra media engines - Part 2 (interrupts) Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 04/30] drm/i915/xehp: Extra media engines - Part 3 (reset) Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 05/30] drm/i915/xehp: Xe_HP forcewake support Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 06/30] drm/i915/xehp: handle new steering options Matt Roper
2021-07-27 19:11 ` Yokoyama, Caz
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 07/30] drm/i915/xehp: Loop over all gslices for INSTDONE processing Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 08/30] drm/i915/xehp: Changes to ss/eu definitions Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 09/30] drm/i915/xehpsdv: Add maximum sseu limits Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 10/30] drm/i915/xehpsdv: Add compute DSS type Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 11/30] drm/i915/xehpsdv: Define steering tables Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 12/30] drm/i915/xehpsdv: Define MOCS table for XeHP SDV Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 13/30] drm/i915/xehpsdv: factor out function to read RP_STATE_CAP Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 14/30] drm/i915/xehpsdv: Read correct RP_STATE_CAP register Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 15/30] drm/i915/dg2: DG2 uses the same sseu limits as XeHP SDV Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 16/30] drm/i915/dg2: Add forcewake table Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 17/30] drm/i915/dg2: Update LNCF steering ranges Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 18/30] drm/i915/dg2: Add SQIDI steering Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 19/30] drm/i915/dg2: Add new LRI reg offsets Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 20/30] drm/i915/dg2: Maintain backward-compatible nested batch behavior Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 21/30] drm/i915/dg2: Report INSTDONE_GEOM values in error state Matt Roper
2021-07-29 15:08 ` Matt Atwood
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 22/30] drm/i915/dg2: Define MOCS table for DG2 Matt Roper
2021-07-29 15:14 ` Matt Atwood
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 23/30] drm/i915/dg2: Add MPLLB programming for SNPS PHY Matt Roper
2021-07-29 15:06 ` Matt Atwood
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 24/30] drm/i915/dg2: Add MPLLB programming for HDMI Matt Roper
2021-07-23 17:42 ` Matt Roper [this message]
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 26/30] drm/i915/dg2: Update modeset sequences Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 27/30] drm/i915/dg2: Wait for SNPS PHY calibration during display init Matt Roper
2021-07-24 4:19 ` kernel test robot
2021-07-24 4:19 ` kernel test robot
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 28/30] drm/i915/dg2: Update lane disable power state during PSR Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 29/30] drm/i915/dg2: Update to bigjoiner path Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 30/30] drm/i915/dg2: Configure PCON in DP pre-enable path Matt Roper
2021-07-23 21:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Begin enabling Xe_HP SDV and DG2 platforms (rev6) Patchwork
2021-07-23 21:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-07-23 21:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
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