From: Lara Lazier <laramglazier@gmail.com>
To: qemu-devel@nongnu.org
Cc: pbonzini@redhat.com, Lara Lazier <laramglazier@gmail.com>
Subject: [PATCH 3/4] target/i386: Added ignore TPR check in ctl_has_irq
Date: Fri, 20 Aug 2021 16:15:57 +0200 [thread overview]
Message-ID: <20210820141558.9031-4-laramglazier@gmail.com> (raw)
In-Reply-To: <20210820141558.9031-1-laramglazier@gmail.com>
The APM2 states that if V_IGN_TPR is nonzero, the current
virtual interrupt ignores the (virtual) TPR.
Signed-off-by: Lara Lazier <laramglazier@gmail.com>
---
target/i386/tcg/sysemu/svm_helper.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/i386/tcg/sysemu/svm_helper.c b/target/i386/tcg/sysemu/svm_helper.c
index 2c44bdb243..cbd3f086c4 100644
--- a/target/i386/tcg/sysemu/svm_helper.c
+++ b/target/i386/tcg/sysemu/svm_helper.c
@@ -83,6 +83,11 @@ static inline bool ctl_has_irq(CPUX86State *env)
int_prio = (env->int_ctl & V_INTR_PRIO_MASK) >> V_INTR_PRIO_SHIFT;
tpr = env->int_ctl & V_TPR_MASK;
+
+ if (env->int_ctl & V_IGN_TPR_MASK) {
+ return env->int_ctl & V_IRQ_MASK;
+ }
+
return (env->int_ctl & V_IRQ_MASK) && (int_prio >= tpr);
}
--
2.25.1
next prev parent reply other threads:[~2021-08-20 14:19 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-20 14:15 [PATCH 0/4] target/i386: V_IRQ masking and V_TPR fixes Lara Lazier
2021-08-20 14:15 ` [PATCH 1/4] target/i386: Moved int_ctl into CPUX86State structure Lara Lazier
2021-08-20 14:15 ` [PATCH 2/4] target/i386: Added VGIF V_IRQ masking capability Lara Lazier
2021-08-20 14:15 ` Lara Lazier [this message]
2021-08-20 14:15 ` [PATCH 4/4] target/i386: Added changed priority check for VIRQ Lara Lazier
-- strict thread matches above, loose matches on Subject: below --
2021-08-18 7:08 [PATCH 0/4] target/i386: V_IRQ masking and V_TPR fixes Lara Lazier
2021-08-18 7:08 ` [PATCH 3/4] target/i386: Added ignore TPR check in ctl_has_irq Lara Lazier
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