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From: "Marek Behún" <kabel@kernel.org>
To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: "Bjorn Helgaas" <bhelgaas@google.com>,
	linux-pci@vger.kernel.org, pali@kernel.org,
	"Marek Behún" <kabel@kernel.org>
Subject: [PATCH 08/14] PCI: aardvark: Fix masking MSI interrupts
Date: Tue, 12 Oct 2021 18:41:39 +0200	[thread overview]
Message-ID: <20211012164145.14126-9-kabel@kernel.org> (raw)
In-Reply-To: <20211012164145.14126-1-kabel@kernel.org>

From: Pali Rohár <pali@kernel.org>

We should not unmask MSIs at setup, but only when kernel asks for them
to be unmasked.

At setup, mask all MSIs, and implement IRQ chip callbacks for masking
and unmasking particular MSIs.

Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver")
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Cc: stable@vger.kernel.org # f21a8b1b6837 ("PCI: aardvark: Move to MSI handling using generic MSI support")
---
 drivers/pci/controller/pci-aardvark.c | 52 ++++++++++++++++++++++++---
 1 file changed, 48 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index ab0a0864a300..1adb4c4b11b5 100644
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -282,6 +282,7 @@ struct advk_pcie {
 	struct irq_domain *msi_inner_domain;
 	struct irq_chip msi_bottom_irq_chip;
 	struct irq_chip msi_irq_chip;
+	raw_spinlock_t msi_irq_lock;
 	struct msi_domain_info msi_domain_info;
 	DECLARE_BITMAP(msi_used, MSI_IRQ_NUM);
 	struct mutex msi_used_lock;
@@ -554,12 +555,10 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
 	advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
 	advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
 
-	/* Disable All ISR0/1 Sources */
+	/* Disable All ISR0/1 and MSI Sources */
 	advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG);
 	advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
-
-	/* Unmask all MSIs */
-	advk_writel(pcie, ~(u32)PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);
+	advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);
 
 	/* Unmask summary MSI interrupt */
 	reg = advk_readl(pcie, PCIE_ISR0_MASK_REG);
@@ -1119,6 +1118,46 @@ static int advk_msi_set_affinity(struct irq_data *irq_data,
 	return -EINVAL;
 }
 
+static void advk_msi_irq_mask(struct irq_data *d)
+{
+	struct advk_pcie *pcie = d->domain->host_data;
+	irq_hw_number_t hwirq = irqd_to_hwirq(d);
+	unsigned long flags;
+	u32 mask;
+
+	raw_spin_lock_irqsave(&pcie->msi_irq_lock, flags);
+	mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
+	mask |= BIT(hwirq);
+	advk_writel(pcie, mask, PCIE_MSI_MASK_REG);
+	raw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags);
+}
+
+static void advk_msi_irq_unmask(struct irq_data *d)
+{
+	struct advk_pcie *pcie = d->domain->host_data;
+	irq_hw_number_t hwirq = irqd_to_hwirq(d);
+	unsigned long flags;
+	u32 mask;
+
+	raw_spin_lock_irqsave(&pcie->msi_irq_lock, flags);
+	mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
+	mask &= ~BIT(hwirq);
+	advk_writel(pcie, mask, PCIE_MSI_MASK_REG);
+	raw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags);
+}
+
+static void advk_msi_top_irq_mask(struct irq_data *d)
+{
+	pci_msi_mask_irq(d);
+	irq_chip_mask_parent(d);
+}
+
+static void advk_msi_top_irq_unmask(struct irq_data *d)
+{
+	pci_msi_unmask_irq(d);
+	irq_chip_unmask_parent(d);
+}
+
 static int advk_msi_irq_domain_alloc(struct irq_domain *domain,
 				     unsigned int virq,
 				     unsigned int nr_irqs, void *args)
@@ -1213,6 +1252,7 @@ static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie)
 	struct msi_domain_info *msi_di;
 	phys_addr_t msi_msg_phys;
 
+	raw_spin_lock_init(&pcie->msi_irq_lock);
 	mutex_init(&pcie->msi_used_lock);
 
 	bottom_ic = &pcie->msi_bottom_irq_chip;
@@ -1220,9 +1260,13 @@ static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie)
 	bottom_ic->name = "MSI";
 	bottom_ic->irq_compose_msi_msg = advk_msi_irq_compose_msi_msg;
 	bottom_ic->irq_set_affinity = advk_msi_set_affinity;
+	bottom_ic->irq_mask = advk_msi_irq_mask;
+	bottom_ic->irq_unmask = advk_msi_irq_unmask;
 
 	msi_ic = &pcie->msi_irq_chip;
 	msi_ic->name = "advk-MSI";
+	msi_ic->irq_mask = advk_msi_top_irq_mask;
+	msi_ic->irq_unmask = advk_msi_top_irq_unmask;
 
 	msi_di = &pcie->msi_domain_info;
 	msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
-- 
2.32.0


  parent reply	other threads:[~2021-10-12 16:42 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-12 16:41 [PATCH 00/14] PCI: aardvark controller fixes BATCH 2 Marek Behún
2021-10-12 16:41 ` [PATCH 01/14] PCI: pci-bridge-emul: Fix emulation of W1C bits Marek Behún
2021-10-12 16:41 ` [PATCH 02/14] PCI: aardvark: Fix return value of MSI domain .alloc() method Marek Behún
2021-10-27 11:26   ` Lorenzo Pieralisi
2021-10-27 11:31     ` Pali Rohár
2021-10-12 16:41 ` [PATCH 03/14] PCI: aardvark: Read all 16-bits from PCIE_MSI_PAYLOAD_REG Marek Behún
2021-10-12 16:41 ` [PATCH 04/14] PCI: aardvark: Fix support for MSI interrupts Marek Behún
2021-10-12 16:41 ` [PATCH 05/14] PCI: aardvark: Fix reading MSI interrupt number Marek Behún
2021-10-12 16:41 ` [PATCH 06/14] PCI: aardvark: Clear all MSIs at setup Marek Behún
2021-10-12 16:41 ` [PATCH 07/14] PCI: aardvark: Refactor unmasking summary MSI interrupt Marek Behún
2021-10-12 16:41 ` Marek Behún [this message]
2021-10-12 16:41 ` [PATCH 09/14] PCI: aardvark: Fix setting MSI address Marek Behún
2021-10-12 16:41 ` [PATCH 10/14] PCI: aardvark: Enable MSI-X support Marek Behún
2021-10-27 14:12   ` Lorenzo Pieralisi
2021-10-27 14:23     ` Pali Rohár
2021-10-28 11:08       ` Lorenzo Pieralisi
2021-10-28 11:13         ` Pali Rohár
2021-10-28 11:30           ` Lorenzo Pieralisi
2021-10-28 11:37             ` Pali Rohár
2021-10-28 15:24               ` Marc Zyngier
2021-10-28 15:29                 ` Pali Rohár
2021-10-28 15:51                 ` Marek Behún
2021-10-28 16:22                   ` Marc Zyngier
2021-10-28 16:25                   ` Marek Behún
2021-10-28 17:00                     ` Marc Zyngier
2021-10-28 17:47                       ` Lorenzo Pieralisi
2021-10-28 18:24                         ` Marek Behún
2021-10-12 16:41 ` [PATCH 11/14] PCI: aardvark: Fix support for bus mastering and PCI_COMMAND on emulated bridge Marek Behún
2021-10-12 16:41 ` [PATCH 12/14] PCI: aardvark: Set PCI Bridge Class Code to PCI Bridge Marek Behún
2021-10-28 18:30   ` Lorenzo Pieralisi
2021-10-28 18:45     ` Pali Rohár
2021-10-28 20:43       ` Bjorn Helgaas
2021-10-12 16:41 ` [PATCH 13/14] PCI: aardvark: Fix support for PCI_BRIDGE_CTL_BUS_RESET on emulated bridge Marek Behún
2021-10-12 16:41 ` [PATCH 14/14] PCI: aardvark: Fix support for PCI_ROM_ADDRESS1 " Marek Behún
2021-10-19 18:36 ` [PATCH 00/14] PCI: aardvark controller fixes BATCH 2 Pali Rohár
2021-10-28 18:33 ` Lorenzo Pieralisi

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