From: Biju Das <biju.das.jz@bp.renesas.com>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
Chris Paterson <Chris.Paterson2@renesas.com>,
Biju Das <biju.das@bp.renesas.com>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH v2 0/4] Add OPP table for RZ/G2L SoC
Date: Fri, 12 Nov 2021 08:09:59 +0000 [thread overview]
Message-ID: <20211112081003.15453-1-biju.das.jz@bp.renesas.com> (raw)
This patch series aims to add OPP table for RZ/G2L SoC.
Supported frequencies are 1.2GHz, 600MHz, 300MHz and 150MHz.
V1->v2:
* Fixed typo cluster1_opp->cluster0_opp
Biju Das (4):
clk: renesas: rzg2l: Add CPG_PL1_DDIV macro
clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV
arm64: dts: renesas: r9a07g044: Sort psci node
arm64: dts: renesas: r9a07g044: Add OPP table
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 36 ++++++++++++++++++++--
drivers/clk/renesas/r9a07g044-cpg.c | 11 ++++++-
drivers/clk/renesas/rzg2l-cpg.h | 2 ++
3 files changed, 45 insertions(+), 4 deletions(-)
--
2.17.1
next reply other threads:[~2021-11-12 8:10 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-12 8:09 Biju Das [this message]
2021-11-12 8:10 ` [PATCH v2 1/4] clk: renesas: rzg2l: Add CPG_PL1_DDIV macro Biju Das
2021-11-18 10:30 ` Geert Uytterhoeven
2021-11-12 8:10 ` [PATCH v2 2/4] clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV Biju Das
2021-11-18 10:31 ` Geert Uytterhoeven
2021-11-12 8:10 ` [PATCH v2 3/4] arm64: dts: renesas: r9a07g044: Sort psci node Biju Das
2021-11-24 14:14 ` Geert Uytterhoeven
2021-11-12 8:10 ` [PATCH v2 4/4] arm64: dts: renesas: r9a07g044: Add OPP table Biju Das
2021-11-24 15:02 ` Geert Uytterhoeven
2021-11-24 15:08 ` Biju Das
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