From: Li Yang <leoyang.li@nxp.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
Rob Herring <robh+dt@kernel.org>,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Cc: Rob Herring <robh@kernel.org>
Subject: [PATCH 2/4] dt-bindings: pci: layerscape-pci: Update the description of SCFG property
Date: Fri, 19 Nov 2021 18:16:19 -0600 [thread overview]
Message-ID: <20211120001621.21246-3-leoyang.li@nxp.com> (raw)
In-Reply-To: <20211120001621.21246-1-leoyang.li@nxp.com>
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Update the description of the second entry of 'fsl,pcie-scfg' property,
as the LS1043A PCIe controller also has some control registers in SCFG
block, while it has 3 controllers.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/pci/layerscape-pci.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index 215d2ee65c83..f1115fcd8088 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -34,7 +34,7 @@ Required properties:
"intr": The interrupt that is asserted for controller interrupts
- fsl,pcie-scfg: Must include two entries.
The first entry must be a link to the SCFG device node
- The second entry must be '0' or '1' based on physical PCIe controller index.
+ The second entry is the physical PCIe controller index starting from '0'.
This is used to get SCFG PEXN registers
- dma-coherent: Indicates that the hardware IP block can ensure the coherency
of the data transferred from/to the IP block. This can avoid the software
--
2.25.1
next prev parent reply other threads:[~2021-11-20 0:16 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-20 0:16 [PATCH 0/4] layerscape-pci binding updates Li Yang
2021-11-20 0:16 ` [PATCH 1/4] dt-bindings: pci: layerscape-pci: Add a optional property big-endian Li Yang
2021-11-20 0:16 ` Li Yang [this message]
2021-11-20 0:16 ` [PATCH 3/4] dt-bindings: pci: layerscape-pci: Add EP mode compatible strings for ls1028a Li Yang
2021-11-30 1:59 ` Rob Herring
2021-11-20 0:16 ` [PATCH 4/4] dt-bindings: pci: layerscape-pci: define aer/pme interrupts Li Yang
2021-11-30 2:02 ` Rob Herring
2021-11-30 3:35 ` Leo Li
2021-11-30 13:47 ` Rob Herring
2021-12-01 23:34 ` Leo Li
2021-11-30 14:22 ` Bjorn Helgaas
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