[PATCH v3 5/7] clk: x86: Fix clk_gate_flags for RV_CLK_GATE

From: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
To: <sboyd@kernel.org>, <rafael@kernel.org>, <linux-clk@vger.kernel.org>
Cc: <Vijendar.Mukunda@amd.com>, <Alexander.Deucher@amd.com>,
	<Basavaraj.Hiregoudar@amd.com>, <Sunil-kumar.Dommati@amd.com>,
	<Mario.Limonciello@amd.com>,
	Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>,
	Michael Turquette <mturquette@baylibre.com>,
	open list <linux-kernel@vger.kernel.org>
Subject: [PATCH v3 5/7] clk: x86: Fix clk_gate_flags for RV_CLK_GATE
Date: Thu, 25 Nov 2021 11:50:34 +0530	[thread overview]
Message-ID: <20211125062036.1185994-6-AjitKumar.Pandey@amd.com> (raw)
In-Reply-To: <20211125062036.1185994-1-AjitKumar.Pandey@amd.com>

In newer SoC we have to clear bit for disabling 48MHz oscillator
clock gate. Remove CLK_GATE_SET_TO_DISABLE flag for proper enable
and disable of 48MHz clock.

Signed-off-by: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
---
 drivers/clk/x86/clk-fch.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/x86/clk-fch.c b/drivers/clk/x86/clk-fch.c
index 4ff2e1b3b3e9..0578297d8322 100644
--- a/drivers/clk/x86/clk-fch.c
+++ b/drivers/clk/x86/clk-fch.c
@@ -82,7 +82,7 @@ static int fch_clk_probe(struct platform_device *pdev)
 
 		hws[CLK_GATE_FIXED] = clk_hw_register_gate(NULL, "oscout1",
 			"clk48MHz", 0, fch_data->base + MISCCLKCNTL1,
-			OSCCLKENB, CLK_GATE_SET_TO_DISABLE, NULL);
+			OSCCLKENB, 0, NULL);
 
 		devm_clk_hw_register_clkdev(&pdev->dev, hws[CLK_GATE_FIXED],
 					    fch_data->name, NULL);
-- 
2.25.1

