From: Huang Rui <ray.huang@amd.com>
To: "Rafael J . Wysocki" <rafael.j.wysocki@intel.com>,
Viresh Kumar <viresh.kumar@linaro.org>,
Shuah Khan <skhan@linuxfoundation.org>,
"Borislav Petkov" <bp@suse.de>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@kernel.org>,
Giovanni Gherdovich <ggherdovich@suse.cz>,
<linux-pm@vger.kernel.org>
Cc: Deepak Sharma <deepak.sharma@amd.com>,
Alex Deucher <alexander.deucher@amd.com>,
Mario Limonciello <mario.limonciello@amd.com>,
Steven Noonan <steven@valvesoftware.com>,
Nathan Fontenot <nathan.fontenot@amd.com>,
Jinzhou Su <Jinzhou.Su@amd.com>,
Xiaojian Du <Xiaojian.Du@amd.com>, <linux-kernel@vger.kernel.org>,
<x86@kernel.org>, Huang Rui <ray.huang@amd.com>
Subject: [PATCH v5 13/22] cpupower: add AMD P-state capability flag
Date: Tue, 30 Nov 2021 20:36:32 +0800 [thread overview]
Message-ID: <20211130123641.1449041-14-ray.huang@amd.com> (raw)
In-Reply-To: <20211130123641.1449041-1-ray.huang@amd.com>
Add AMD P-state capability flag in cpupower to indicate AMD new P-state
kernel module support on Ryzen processors.
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
tools/power/cpupower/utils/helpers/helpers.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/power/cpupower/utils/helpers/helpers.h b/tools/power/cpupower/utils/helpers/helpers.h
index 33ffacee7fcb..b4813efdfb00 100644
--- a/tools/power/cpupower/utils/helpers/helpers.h
+++ b/tools/power/cpupower/utils/helpers/helpers.h
@@ -73,6 +73,7 @@ enum cpupower_cpu_vendor {X86_VENDOR_UNKNOWN = 0, X86_VENDOR_INTEL,
#define CPUPOWER_CAP_AMD_HW_PSTATE 0x00000100
#define CPUPOWER_CAP_AMD_PSTATEDEF 0x00000200
#define CPUPOWER_CAP_AMD_CPB_MSR 0x00000400
+#define CPUPOWER_CAP_AMD_PSTATE 0x00000800
#define CPUPOWER_AMD_CPBDIS 0x02000000
--
2.25.1
next prev parent reply other threads:[~2021-11-30 12:38 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-30 12:36 [PATCH v5 00/22] cpufreq: introduce a new AMD CPU frequency control mechanism Huang Rui
2021-11-30 12:36 ` [PATCH v5 01/22] x86/cpufeatures: add AMD Collaborative Processor Performance Control feature flag Huang Rui
2021-11-30 12:36 ` [PATCH v5 02/22] x86/msr: add AMD CPPC MSR definitions Huang Rui
2021-12-16 17:23 ` Rafael J. Wysocki
2021-12-17 3:09 ` Huang Rui
2021-11-30 12:36 ` [PATCH v5 03/22] ACPI: CPPC: implement support for SystemIO registers Huang Rui
2021-12-16 17:40 ` Rafael J. Wysocki
2021-12-17 4:30 ` Huang Rui
2021-11-30 12:36 ` [PATCH v5 04/22] ACPI: CPPC: Check present CPUs for determining _CPC is valid Huang Rui
2021-11-30 12:36 ` [PATCH v5 05/22] ACPI: CPPC: add cppc enable register function Huang Rui
2021-11-30 12:36 ` [PATCH v5 06/22] cpufreq: amd: introduce a new amd pstate driver to support future processors Huang Rui
2021-12-16 17:59 ` Rafael J. Wysocki
2021-12-17 7:34 ` Huang Rui
2021-12-17 14:03 ` Rafael J. Wysocki
2021-11-30 12:36 ` [PATCH v5 07/22] cpufreq: amd: add fast switch function for amd-pstate Huang Rui
2021-11-30 12:36 ` [PATCH v5 08/22] cpufreq: amd: introduce the support for the processors with shared memory solution Huang Rui
2021-12-16 18:04 ` Rafael J. Wysocki
2021-12-17 7:37 ` Huang Rui
2021-11-30 12:36 ` [PATCH v5 09/22] cpufreq: amd: add trace for amd-pstate module Huang Rui
2021-12-16 18:12 ` Rafael J. Wysocki
2021-12-17 7:52 ` Huang Rui
2021-12-17 14:05 ` Rafael J. Wysocki
2021-11-30 12:36 ` [PATCH v5 10/22] cpufreq: amd: add boost mode support for amd-pstate Huang Rui
2021-11-30 12:36 ` [PATCH v5 11/22] cpufreq: amd: add amd-pstate frequencies attributes Huang Rui
2021-11-30 12:36 ` [PATCH v5 12/22] cpufreq: amd: add amd-pstate performance attributes Huang Rui
2021-11-30 12:36 ` Huang Rui [this message]
2021-11-30 12:36 ` [PATCH v5 14/22] cpupower: add the function to check amd-pstate enabled Huang Rui
2021-11-30 12:36 ` [PATCH v5 15/22] cpupower: initial AMD P-state capability Huang Rui
2021-11-30 12:36 ` [PATCH v5 16/22] cpupower: add the function to get the sysfs value from specific table Huang Rui
2021-11-30 12:36 ` [PATCH v5 17/22] cpupower: introduce acpi cppc library Huang Rui
2021-11-30 12:36 ` [PATCH v5 18/22] cpupower: add amd-pstate sysfs definition and access helper Huang Rui
2021-11-30 12:36 ` [PATCH v5 19/22] cpupower: enable boost state support for amd-pstate module Huang Rui
2021-11-30 12:36 ` [PATCH v5 20/22] cpupower: move print_speed function into misc helper Huang Rui
2021-11-30 12:36 ` [PATCH v5 21/22] cpupower: print amd-pstate information on cpupower Huang Rui
2021-11-30 12:36 ` [PATCH v5 22/22] Documentation: amd-pstate: add amd-pstate driver introduction Huang Rui
2021-12-16 18:20 ` [PATCH v5 00/22] cpufreq: introduce a new AMD CPU frequency control mechanism Rafael J. Wysocki
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211130123641.1449041-14-ray.huang@amd.com \
--to=ray.huang@amd.com \
--cc=Jinzhou.Su@amd.com \
--cc=Xiaojian.Du@amd.com \
--cc=alexander.deucher@amd.com \
--cc=bp@suse.de \
--cc=deepak.sharma@amd.com \
--cc=ggherdovich@suse.cz \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=mario.limonciello@amd.com \
--cc=mingo@kernel.org \
--cc=nathan.fontenot@amd.com \
--cc=peterz@infradead.org \
--cc=rafael.j.wysocki@intel.com \
--cc=skhan@linuxfoundation.org \
--cc=steven@valvesoftware.com \
--cc=viresh.kumar@linaro.org \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.