From: Biju Das <biju.das.jz@bp.renesas.com>
To: Rob Herring <robh+dt@kernel.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
Chris Paterson <Chris.Paterson2@renesas.com>,
Biju Das <biju.das@bp.renesas.com>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH 4/4] arm64: dts: renesas: rzg2lc-smarc: Enable RSPI1 on carrier board
Date: Mon, 7 Mar 2022 19:24:36 +0000 [thread overview]
Message-ID: <20220307192436.13237-5-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20220307192436.13237-1-biju.das.jz@bp.renesas.com>
RSPI1 (SPI1) interface is available on PMOD0 connector (J1) on the
carrier board. This patch adds pinmux and spi1 nodes to the carrier
board dtsi file and drops deleting pinctl* properties from DTS file.
RSPI1 interface is tested by setting the macro SW_RSPI_CAN to 0.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts | 6 ------
arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 7 +++++++
arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 8 ++++++++
3 files changed, 15 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
index 74a2f2bade10..fc34058002e2 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
@@ -13,9 +13,3 @@
model = "Renesas SMARC EVK based on r9a07g044c2";
compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044";
};
-
-&spi1 {
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- status = "disabled";
-};
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
index d275a55333e3..a78a8def363e 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
@@ -106,6 +106,13 @@
input-enable;
};
+ spi1_pins: spi1 {
+ pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */
+ <RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */
+ <RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */
+ <RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */
+ };
+
ssi0_pins: ssi0 {
pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */
<RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
index f73b4acb8f9e..292513635baf 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
@@ -74,6 +74,14 @@
};
};
+#if (!SW_RSPI_CAN)
+&spi1 {
+ pinctrl-0 = <&spi1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+#endif
+
/*
* To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board
* SW1 should be at position 2->3 so that SER0_CTS# line is activated
--
2.17.1
next prev parent reply other threads:[~2022-03-07 19:24 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-07 19:24 [PATCH 0/4] Enable RZ/G2LC OSTM, QSPI0, RSPI and Voltage regulator for GPU Biju Das
2022-03-07 19:24 ` [PATCH 1/4] arm64: dts: renesas: rzg2lc-smarc-som: Enable serial NOR flash Biju Das
2022-03-18 13:13 ` Geert Uytterhoeven
2022-03-07 19:24 ` [PATCH 2/4] arm64: dts: renesas: rzg2lc-smarc-som: Enable OSTM Biju Das
2022-03-18 13:14 ` Geert Uytterhoeven
2022-03-07 19:24 ` [PATCH 3/4] arm64: dts: renesas: rzg2lc-smarc-som: Add vdd core regulator Biju Das
2022-03-18 13:14 ` Geert Uytterhoeven
2022-03-07 19:24 ` Biju Das [this message]
2022-03-18 13:15 ` [PATCH 4/4] arm64: dts: renesas: rzg2lc-smarc: Enable RSPI1 on carrier board Geert Uytterhoeven
2022-03-18 13:24 ` Biju Das
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