All of lore.kernel.org
 help / color / mirror / Atom feed
From: ira.weiny@intel.com
To: Dan Williams <dan.j.williams@intel.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Alison Schofield <alison.schofield@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	Ira Weiny <ira.weiny@intel.com>,
	Ben Widawsky <ben.widawsky@intel.com>,
	linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org,
	linux-pci@vger.kernel.org
Subject: [PATCH V7 08/10] cxl/cdat: Introduce cxl_cdat_valid()
Date: Wed, 30 Mar 2022 16:59:18 -0700	[thread overview]
Message-ID: <20220330235920.2800929-9-ira.weiny@intel.com> (raw)
In-Reply-To: <20220330235920.2800929-1-ira.weiny@intel.com>

From: Ira Weiny <ira.weiny@intel.com>

The CDAT data is protected by a checksum and should be the proper
length.

Introduce cxl_cdat_valid() to validate the data.  While at it check and
store the sequence number.

Signed-off-by: Ira Weiny <ira.weiny@intel.com>

---
Changes from V6
	Change name to cxl_cdat_valid() as this validates all the CDAT
		data not just the header
	Add error and debug prints

Changes from V5
	New patch, split out
	Update cdat_hdr_valid()
		Remove revision and cs field parsing
			There is no point in these
		Add seq check and debug print.
---
 drivers/cxl/cdat.h |  2 ++
 drivers/cxl/pci.c  | 36 ++++++++++++++++++++++++++++++++++++
 2 files changed, 38 insertions(+)

diff --git a/drivers/cxl/cdat.h b/drivers/cxl/cdat.h
index 4722b6bbbaf0..a7725d26f2d2 100644
--- a/drivers/cxl/cdat.h
+++ b/drivers/cxl/cdat.h
@@ -88,10 +88,12 @@
  *
  * @table: cache of CDAT table
  * @length: length of cached CDAT table
+ * @seq: Last read Sequence number of the CDAT table
  */
 struct cxl_cdat {
 	void *table;
 	size_t length;
+	u32 seq;
 };
 
 #endif /* !__CXL_CDAT_H__ */
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index a1d500381438..ddd6b705fd67 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -762,6 +762,40 @@ static int cxl_setup_doe_devices(struct cxl_dev_state *cxlds)
 	return 0;
 }
 
+static bool cxl_cdat_valid(struct device *dev, struct cxl_cdat *cdat)
+{
+	u32 *table = cdat->table;
+	u8 *data8 = cdat->table;
+	u32 length, seq;
+	u8 check;
+	int i;
+
+	length = FIELD_GET(CDAT_HEADER_DW0_LENGTH, table[0]);
+	if ((length < CDAT_HEADER_LENGTH_BYTES) || (length > cdat->length)) {
+		dev_err(dev, "Invalid length %u (%lu-%lu)\n", length,
+			CDAT_HEADER_LENGTH_BYTES, cdat->length);
+		return false;
+	}
+
+	for (check = 0, i = 0; i < length; i++)
+		check += data8[i];
+
+	dev_dbg(dev, "CDAT length %u CS %u\n", length, check);
+	if (check != 0) {
+		dev_err(dev, "Invalid checksum %u\n", check);
+		return false;
+	}
+
+	seq = FIELD_GET(CDAT_HEADER_DW3_SEQUENCE, table[3]);
+	/* Store the sequence for now. */
+	if (cdat->seq != seq) {
+		dev_info(dev, "CDAT seq change %x -> %x\n", cdat->seq, seq);
+		cdat->seq = seq;
+	}
+
+	return true;
+}
+
 #define CDAT_DOE_REQ(entry_handle)					\
 	(FIELD_PREP(CXL_DOE_TABLE_ACCESS_REQ_CODE,			\
 		    CXL_DOE_TABLE_ACCESS_REQ_CODE_READ) |		\
@@ -873,6 +907,8 @@ static int cxl_cdat_read_table(struct cxl_dev_state *cxlds,
 
 release_driver:
 	cxl_pci_doe_put_drv(doe_dev);
+	if (!rc && !cxl_cdat_valid(cxlds->dev, cdat))
+		return -EIO;
 	return rc;
 }
 
-- 
2.35.1


  parent reply	other threads:[~2022-03-31  0:00 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-30 23:59 [PATCH V7 00/10] CXL: Read CDAT and DSMAS data from the device ira.weiny
2022-03-30 23:59 ` [PATCH V7 01/10] PCI: Add vendor ID for the PCI SIG ira.weiny
2022-03-30 23:59 ` [PATCH V7 02/10] PCI: Replace magic constant for PCI Sig Vendor ID ira.weiny
2022-03-30 23:59 ` [PATCH V7 03/10] PCI: Create PCI library functions in support of DOE mailboxes ira.weiny
2022-03-31  5:50   ` Christoph Hellwig
2022-03-31 15:19     ` Ira Weiny
2022-04-02 14:48       ` Lukas Wunner
2022-04-05 23:22         ` Ira Weiny
2022-04-06 10:11           ` Jonathan Cameron
2022-04-06 21:23             ` Ira Weiny
2022-04-07 16:01               ` Bjorn Helgaas
2022-03-30 23:59 ` [PATCH V7 04/10] cxl/pci: Create auxiliary devices for each DOE mailbox ira.weiny
2022-04-29 15:33   ` Jonathan Cameron
2022-03-30 23:59 ` [PATCH V7 05/10] cxl/pci: Create DOE auxiliary driver ira.weiny
2022-03-30 23:59 ` [PATCH V7 06/10] cxl/pci: Find the DOE mailbox which supports CDAT ira.weiny
2022-03-30 23:59 ` [PATCH V7 07/10] cxl/mem: Read CDAT table ira.weiny
2022-03-30 23:59 ` ira.weiny [this message]
2022-03-30 23:59 ` [PATCH V7 09/10] cxl/mem: Retry reading CDAT on failure ira.weiny
2022-03-30 23:59 ` [PATCH V7 10/10] cxl/port: Parse out DSMAS data from CDAT table ira.weiny

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20220330235920.2800929-9-ira.weiny@intel.com \
    --to=ira.weiny@intel.com \
    --cc=Jonathan.Cameron@huawei.com \
    --cc=alison.schofield@intel.com \
    --cc=ben.widawsky@intel.com \
    --cc=bhelgaas@google.com \
    --cc=dan.j.williams@intel.com \
    --cc=linux-cxl@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=vishal.l.verma@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.